Andes Technology Adopts Cadence Digital Front-End Low-Power Flow



Andes Deploys the Common Power Format and Cadence Digital Solution to Provide Its Customers a Scalable, Configurable Low-Power Management Framework

SAN JOSE, CA and TAIPEI, TAIWAN–(Marketwire – August 30, 2010) –  Cadence Design Systems, Inc. (NASDAQ: CDNS), a leader in global electronic design innovation, today announced that Andes Technology, a Taiwanese provider of high-performance, low-power 32-bit processor IP and SoC platforms, has adopted the Cadence® digital front-end low-power design flow. The flow, based on the Common Power Format (CPF), deploys Cadence synthesis, simulation and formal verification technology. It enables Andes to provide its customers a scalable and configurable low-power management framework that blends hardware and software solutions for sophisticated power domain partitions and power scaling schemes.

“Providing low-power products is essential to any company determined to be a serious competitor in embedded system applications,” said James Lai, associate vice president of Andes. “Teaming with Cadence, we were able to shorten the development cycles for our SoC platform IP products implementing the AndesCool™ low-power management feature, built on top of the CPF design and verification flows. By integrating CPF into our AndesCool framework, we are now getting ready to provide our customers a robust and flexible reference solution to help them hit their low-power targets efficiently and consistently.”

The Cadence approach to low-power design is based on a single, consistent notion of power intent that is pervasive through design, verification and analysis, and is production proven with hundreds of advanced low-power tapeouts. The Cadence CPF flow provides Andes an efficient path to initiate the development of its AndesCool low-power management framework. The flow provides an integrated power-intent specification throughout the entire ASIC design flow that has helped shorten Andes’ development cycle dramatically by removing replicated integration and verification efforts throughout the development stages. It also has saved Andes time by reducing design respins caused by the lack of power intent specifications in the old methodology.

The Cadence technology adopted by Andes includes Encounter RTL Compiler, Encounter® Conformal® Low Power and Incisive® Enterprise Simulator.

“Andes’ adoption of the Cadence low-power flow not only helped the company achieve its aggressive power goals for its SoC platform IP, but will enable Andes to help its customers enhance development effectiveness, too,” said Pete Hardee, product marketing director at Cadence. “Andes’ approach is a great example of living the EDA360 vision as companies turn to solutions that pan Silicon, SoC and System Realization to gain a competitive edge.”

About Cadence
Cadence enables global electronic design innovation and plays an essential role in the creation of today’s integrated circuits and electronics. Customers use Cadence software and hardware, methodologies, and services to design and verify advanced semiconductors, consumer electronics, networking and telecommunications equipment, and computer systems. The company is headquartered in San Jose, Calif., with sales offices, design centers, and research facilities around the world to serve the global electronics industry. More information about the company, its products, and services is available at www.cadence.com.

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