Altera Rolls Out Arria V Early Power Estimator Tool



SAN JOSE, Calif., Sept. 7, 2011 /PRNewswire/ — Altera Corporation (NASDAQ: ALTR) today announced its new Arria® V PowerPlay Early Power Estimator (EPE) tool in conjunction with the “How Low Can You Go with Arria V FPGAs?” drawing. The Arria V EPE allows designers to quickly and accurately evaluate a system’s power consumption, thereby accelerating development time and meeting power budgets. U.S. system designers can enter to win the grand prize of an Arria V FPGA Development Kit, or biweekly drawings for a BeMicro Development Kit or an Altera® polo shirt just by submitting an Arria V EPE estimate spreadsheet by December 19, 2011. See the drawing rules for eligibility, conditions and submission instructions. This drawing is valid only to residents of the continental United States.

The Arria V EPE estimates current draw and power consumption, which can be modeled based on the real system’s operating conditions, board type profiles and cooling techniques. The tool outputs not only the total power consumption, but also the power used by each set of elements in the FPGA, the static power, current consumed by each power rail, the junction temperature, and the theta JA, representing the thermal efficiency of the FPGA.

By trying out the easy-to-use Arria V EPE, system designers can determine just how low their power can go using Arria V FPGAs. To start, users download the Arria V EPE and input the design parameters such as logic, clock frequency and I/Os. The tool then will quickly estimate the power requirements the proposed design will consume. This estimate allows designers to accurately evaluate the power consumption savings that can be achieved using Arria V FPGAs. In addition, designers can see how Altera used the Arria V EPE to benchmark power consumption and get tips on how to model a design at the Arria V FPGA Power Wiki.

Arria V FPGAs deliver the lowest total power for midrange applications with an optimized balance between power, performance and price, based on Altera’s tailored approach to the 28-nm device portfolio. This approach meets customers’ unique design requirements because a one-size-fits-all approach does not work for increasingly complex designs. Altera’s 28LP process provides the ability to have the lowest static power for midrange FPGAs and receive high system performance from a fast FPGA fabric, fast I/Os and fast transceiver data rates. The Arria V architecture has been tailored to maintain current performance while providing a huge power savings.

About Altera

Altera programmable solutions enable system and semiconductor companies to rapidly and cost-effectively innovate, differentiate and win in their markets. Find out more about Altera’s FPGA, CPLD and ASIC devices at www.altera.com. Follow Altera via Facebook, RSS and Twitter.

Contact Information

Altera

101 Innovation Drive
San Jose, CA, 95134
USA

tele: (408) 544-7000
http://www.altera.com/

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