Optimizing and Simplifying the Process: Q&A with a Systems/IC Architect on Ultra-Low-Power-Design

What will it take for ultra-low-power designs to become more prevalent—that’s one of the questions fielded here (think commitment to sub-threshhold design) but far from the only one.

Our thanks to Andy Kelly, Systems/IC Architect, Cactus Semiconductor, Inc., for his insights and observations on topics including accomplishing device miniaturization, prioritizing requirements and top-down design and simulation tools, among other subjects.

EECatalog: In what areas are you finding designers struggling most as they strive to optimize and simplify the design process, particularly when working on ultra-low power designs?

andy_kellyAndy Kelly, Cactus Semiconductor: The biggest challenge I see with our full-custom IC design projects is on the requirements definition—more so than in the design execution. Since our devices are fully customized, customers often start off under the assumption that they can have the highest performance AND the lowest power consumption AND the smallest circuit area. In practice, these requirements all need to be prioritized, and compromises must be made in order to reach a set of requirements that can be met on a reasonable budget and schedule.

EECatalog: What is being done within the semiconductor industry in general to address the challenges named in Question (1) and what role more specifically is Cactus playing?

Kelly, Cactus Semiconductor: The industry as a whole has made great progress in the development of “top-down” design and simulation tools. These tools allow the system and IC design teams to build up a virtual circuit based on behavioral models. These models can be integrated into higher-level system simulations. Then tradeoffs can be modeled and assessed with significantly less effort than with detailed circuit design. Once the behavioral modeling is complete and the requirements are finalized, the detailed circuit design can proceed with significantly better efficiency. At Cactus Semiconductor, we recognize the requirements definition as the key to success, and we include a “Definition & Specification” phase at the beginning of every project to ensure we have a good set of requirements before starting the detailed design phase.

EECatalog: What’s the argument for considering a custom ASIC design for a design that requires device miniaturization? What myths, or misconceptions, if any, have you had to dispel in making this argument?

Kelly, Cactus Semiconductor: There are two primary arguments in favor of custom IC design over standard product design. The first is that the custom design can integrate multiple functions in a single IC. This eliminates the packaging and IO overhead of numerous components, devices, and interconnects. It results in an ASIC footprint that can be an order of magnitude smaller than the footprint of the standard products it replaces. The second argument is that custom IC design enables us to design very specifically to the required function and performance. In contrast, standard product designs use a collection of devices and components meant for general purpose, and thus typically result in a sub-optimal design that inevitably consumes more power than an ASIC equivalent. In the case of implantable or hand-held devices, the system’s battery is typically the single largest component in the system. As such, a full-custom IC design can often lead to huge reductions in device size due to battery size reduction. The biggest myth we have to dispel on a fairly regular basis is the idea that once you commit to a full-custom design, you should strive to maximize integration. While this approach logically makes sense, in practice, it is very uncommon for the maximized integration approach to lead to the best overall solution. At Cactus Semiconductor, we strive for “smart integration” in favor of “maximum integration.”

EECatalog: Could you define in more detail what is meant by “smart integration?”

Kelly, Cactus Semiconductor: “Smart Integration” involves a systematic definition of all system requirements, followed by an assessment of optional paths to meeting each requirement. Finally, a tradeoff of each path is covered that includes; electrical performance, power consumption, device size, development cost and schedule, component cost, reliability and others. When all of these factors are weighed for each system requirement, we often conclude that a mix of custom ICs and standard products will result in the optimal solution. This is what we refer to as “smart integration.” A common example of smart integration comprises a system partition that includes a standard microcontroller along with a full-custom ASIC. While the microcontroller functions could be integrated if necessary, we have found that the performance, power, size, and cost of some newer microcontroller parts make them extremely attractive, and difficult to justify full integration.

EECatalog: Can the principles of smart integration apply across a number of areas where ultra-low-power and high performance design is needed, e.g., medical, gaming, digital signage, industrial control and automation?

Kelly, Cactus Semiconductor: In my opinion, the principles of smart integration can apply to any discipline or market. The end results will vary greatly due to the different system requirements, but smart integration is a process, not a result—and that process can and should be used for any project.

EECatalog: What, if anything, are you seeing as problems or challenges that are not getting their fair share of attention in the area of ultra-low-power design?

Kelly, Cactus Semiconductor: For ultra-low-power designs, we often need to apply design techniques whereby the MOS devices in a circuit are operated in their sub-threshold region. Since this is not the operating state of devices for mainstream and traditional designs, the device modeling and circuit library availability is lacking. I have recently seen progress in this area, but for most process technologies, committing to a completely sub-threshold design typically involves some extra development effort and risk. This translates into higher development cost and longer development schedules. If the models and circuit libraries supporting sub-threshold operation were to reach the level that standard operation has achieved, I think we would see a much greater emphasis on this design approach, and ultra-low-power designs would be more prevalent.

Anne Fisher is managing editor of EECatalog.com. Her experience has included opportunities to cover a wide range of embedded solutions in the PICMG ecosystem as well as other technologies. Anne enjoys bringing embedded designers and developers solutions to technology challenges as described by their peers as well as insight and analysis from industry leaders. She can be reached at afisher@extensionmedia.com

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