SoC Makers Recognizing the High Stakes in Low Power
Q&A with Sonics CTO Drew Wingard
The opportunities afforded by industrial, medical, consumer and mobile sectors—especially as the IoT grows—are closely entwined with power management.
What time is it? Dr. Drew Wingard, CTO of on-chip networks maker Sonics, says that had he not powered off his smart watch before boarding an international flight, the device would not have been able to answer that question upon arrival—it couldn’t hold time for more than a day. During a recent EECatalog interview, Wingard spoke about the factors that led to the “crazy” idea of a smart watch that can’t tell time, where the opportunities to conserve power are to be found, and how battery thresholds enable markets. Edited excerpts of the interview follow.
EECatalog: What makes for a good understanding of power partitioning decisions?
Wingard, Sonics: It certainly has a lot to do with trying to understand the use models, in many cases, not just of the chip, but also of the system in which the chip is going to be used. This is much more difficult to do when building a chip that is truly general-purpose.
Something interesting about the SoC space is that we don’t see that many chips that are designed in a truly general-purpose way. In many respects we are fortunate—in others cursed—that SoCs tend to be pretty application-specific. Say I am building a chip that is going to be the application processor inside a mobile phone. That [choice] defines a set of use cases for the end phone that we can take advantage of in trying to make these choices, or, say it’s going to be a TV processor that is going to be for adding Internet capability. That would have another set of use cases associated with it. The best SoC architects build libraries of knowledge over time about what’s required of the systems the chip is going to plug into.
It is relatively rare that you get a new company trying to attack an SoC application these days. Most companies work with what they’ve learned over the years of integrating ever-larger system chips, making most designs at some level evolutionary. A company may make radical changes in its architecture, but this occurs within the framework of understanding this library of knowledge about what the likely use models are going to be.
EECatalog: Has the answer to what makes for the most effective power management strategy for a multicore SoC changed?
Wingard, Sonics: Before leakage was a problem, when the transistors used to shut off all the way, the biggest user of power in the chip was switching, and power management had everything to do with clock management.
That’s still a very important technique today, but leakage has become such an issue, there is now a whole host of additional techniques to deal with it. At the level of the underlying silicon, that has always been the case, but of course the manufacturing process doesn’t always give us the same transistors on every chip. Sometimes we are at the corner where the transistors are relatively slow. For power [considerations] slower transistors are better because they have lower current. And that means their leakage current tends to be low.
For speed, of course fast transistors are better, but fast transistors are the ones that tend to have the highest leakage. One technique that can be deployed, although it is not very friendly for FinFETs, is to change the voltage of the well contact. You can change the electrical characteristics of a transistor by using the fourth terminal that people rarely think about. There has been a lot of work done to try to optimize the combination of frequency and leakage by playing with the voltage on that terminal. That [playing with the voltage on the terminal] was something that was very attractive for eight of the past 10 years, but now, as the focus has shifted to 3D transistors in the form of FinFETS and others, it turns out that fourth terminal is not available to us to play with any more, so we are using other techniques.
Another technique that has become very common is to optimize the supply voltage of a circuit to match the frequency that it needed to operate at, and so people talk about techniques like dynamic voltage and frequency scaling.
If software can determine that the total loading on your computer is lower than what is needed at peak, it can slow down the clock, which helps save some power, but you can save even more power and a lot of leakage by reducing the supply voltage at the same time. By switching off whole banks of circuits, instead of just stopping their clocks when they are idle, you can cut the power to them and eliminate leakage altogether—this is another technique practiced more frequently today.
The technologies I’ve just noted have substantial implementation costs associated with them, so designers have to be careful about where and when to apply them. This is where the knowledge of use cases and the role of the different IP cores in the chip in those use cases becomes important.
EECatalog: What are the characteristics you would find in companies that are successful in creating ultra-low power solutions?
Wingard, Sonics: While we have been talking about power as being a design imperative for 10 years now, it is still the case for most design teams that power is not a primary design concern—that clearly does not make sense, but it is still the reality. So the people who tend to do the best designs for low power are those who think about low power continuously through their architecture, design and verification processes. There are design teams who do not wait for a characterization tool to tell them after they are done how much power they used, but who [instead] design low power in as part of the goal and continuously track how well they are doing versus their power goal.
Now, there are limitations in the ability of—and certainly in the use of—EDA tools to help in that process. The state of the art in EDA tooling around this is not anywhere near as advanced as it is around the design and verification challenge.
Wingard, Sonics: Because there has not been as much effort. It boils down to where the semiconductor designers are willing to spend their dollars—it’s not that EDA companies are not willing to build those tools, I think that the market for those tools has not yet fully emerged. There have been companies trying, and there have been some companies who have failed trying to provide tools for doing better architectural low-power analysis. It is not because their solutions didn’t work, but because for most organizations designing for low power remains an afterthought.
EECatalog: What will cause it not to be an afterthought?
Wingard, Sonics: One factor could be this crazy idea of these smart watches that you have to plug in everyday. I had a watch that could not hold time for more than a day, and I had to power it off before I got on an international flight because I knew that if I left it on, it would not know the time when I landed at my destination—that is kind of crazy, right?
We’ve seen that battery lifetime thresholds enable markets. [Say] I have a great wireless communications device that has to be plugged in all the time— that kind of defeats the purpose of having it be wireless.
There have been domains for many years where there was incredibly great work done around low-power design. The original digital watch industry did some fantastic work. They built chips that used transistors in strange regions of operation that normal digital people don’t think of because they could do it and make digital watches that lasted for a couple of years on a battery. Now the question is what part of this mammoth opportunity that we know by the umbrella term “Internet of Things” will drive people to look at the low power issue in a new way?
Certainly the first generation of chips that were all targeting wearable applications is where we saw companies who had largely failed designing cell phone processors trying to dumb down their chips for some of these imaging-capable wearable devices with graphic displays—those have not worked very well. You can make the strong argument that it is form factor and battery life that are two reasons why they haven’t worked very well.
Medical wearables is an area where there are considerable privacy and security concerns, but some people have discussed pretty publicly that maybe the time when wearables take off is when the insurance company determines that it save them money to buy you something to monitor your health.
EECatalog: Where are you seeing the need for better communication among various interest groups so as to achieve a “rising tide lifts all boats” effect with regard to ultra low power?
Wingard, Sonics: Large semiconductor companies [have already] worked very productively with the EDA companies to come up with a set of power intent formats. IEEE 1801 allows for the low-level design of things that have multiple power islands and are done in a fashion that is electrically safe. While there will probably be some small enhancements over the years, this important and productive work is largely done.
Today, it is not about the implementation of these techniques, it is about helping design teams understand how many power islands should they create, how many clock domains should they create. It goes back to some analysis challenges.
Of course most SoCs are built out of a lot of reused components which are licensed in from the outside, and then some new logic, and one thing that we are almost completely bare on is: how do we come up with some standards for the interfaces that signal “hey, I am idle, you might want to shut me down” or “hey, I want to shut you down, are you okay with me doing that?” There are some basic communication interfaces that make dynamic power control much easier to implement when you are looking at an SoC that may have 150 blocks on it. Dealing with vendor- or company-proprietary interfaces or trying to figure out how to add an interface around a block that was designed without this kind of cycling ends up being quite a daunting task for the person trying to integrate an SoC, and I think as we move forward we should start to see some real work in that area.
EECatalog: Should we anticipate announcements from Sonics on the ultra-low power front?
Wingard, Sonics: I would hope so. First we have to make sure that we design our on-chip networks and our other IP products so that they use as little power as we can by aggressively employing conventional techniques. And I think our customers would report that [compared to] competing solutions we use between 40% and 80% less power for the same amount of work.
Our announcement last year that we had been awarded a patent on some active power management technology hints at an area in which we are very interested. I would encourage your readers to watch for more information from Sonics in this area!
Anne Fisher is managing editor of EECatalog.com. Her experience has included opportunities to cover a wide range of embedded solutions in the PICMG ecosystem as well as other technologies. Anne enjoys bringing embedded designers and developers solutions to technology challenges as described by their peers as well as insight and analysis from industry leaders. She can be reached at firstname.lastname@example.org