FD-SOI Process Yields Processor on a Power-Sipping IoT Budget

IoT finds new life with technology that adapts to the often intermittent, bursty high-performance followed by periods of ultra-low power that IoT set-ups may often demand.

For Internet of Things (IoT) devices, proficient energy management and ultra-low power consumption are critical. One area of concern for conserving power lies within the IoT device’s embedded processor.

The main factors contributing to the power efficiency of the processor include:

  • Technology node
    • Wide dynamic voltage range
    • Low leakage
  • Architecture
    • Heterogeneous processing
    • Power Islands
    • Power mode enablement

Of all the parameters, the process technology is fundamental to power efficiency. One recent process technology that has dramatically improved the landscape for power efficiency is Fully Depleted Silicon On Insulator (FD-SOI).

Processor Technology and Core Architecture
Shrinking process technologies allow for higher integration along with lower run time power at a cost of increased static power due to higher leakage.

Figure 1: NXP has unique FD-SOI enablement in a large dynamic gate and body biasing voltage range, low quiescent current bias generators, and enhanced Analog-to-Digital Converter (ADC) performance.

FD-SOI can prevent the trend of growing leakage through the following methods:

  • Leveraging existing manufacturing techniques to apply an ultra-thin buried oxide layer on top of the silicon base (see Figure 1). The transistor channel is formed with a thin layer of silicon above the oxide layer. The buried oxide layer curtails the flow of electrons between the source and drain, which naturally reduces leakage current.
  • The thinner transistor channel also allows for the use of lower Vdd voltages through better electrostatic control.

Additionally, FD-SOI’s ability to Reverse Body Bias (RBB), applying a negative voltage on the back side of the channel, can create a barrier preventing the movement of electrons.

Even though the shrinking process technology naturally allows for lower dynamic currents, FD-SOI can go a step further in reducing dynamic power through the following:

  • Wide Vdd voltage range, allowing for operation at very low power levels.
  • Forward Body Biasing (FBB) reduces the operating Vdd voltage for a given frequency. Instead of impeding the movement of electrons due to RBB, now electrons are encouraged to move.
  • FD-SOI construction results in lower parasitics, lowering the dynamic power of the transistor.

Figure 2: Body-biasing means that the device can be faster when required and more energy efficient when performance isn’t critical.

As process technologies have gotten smaller, other trade-offs have arisen. Indeed, designing for analog signals has become more complicated. However, FD-SOI relaxes density rules, allows higher gain, a closer match of components (which reduces the need for compensation during layout), and achieves lower 1/f noise [1].

The industry is hitting a physical wall as miniaturization continues to approach ever-smaller nanometer nodes. The physics of electricity at nanometer scale have begun to interfere with our design dreams of better, faster, smaller, cheaper, and more power-efficient chips. The smaller the architecture, the more significant the potential is for latch-up, as transistors within integrated chips are spaced physically closer to each other. Latch-up provides a potentially catastrophic alternate path for current flow, and until power is cycled to the chip, latch-up is present even after the condition that caused it is no longer present. However, the ultra-thin buried oxide layer utilized in the FD-SOI process provides immunity from latch-up.

Features Enabled by FD-SOI
Taking a markedly different approach than do vendors who rebrand cell phone or tablet chips as ‘IoT SoCs,’ NXP has designed the new i.MX 7ULP applications processor from the ground up as an IoT device—choosing a low-power 28nm FD-SOI process node, a set of power-sensitive peripherals, and an architecture featuring dual power domains based on the Cortex-A7 and the Cortex-M4 cores.

By leveraging the process technology, power friendly heterogeneous architecture, and multiple smart power modes, the processor can achieve impressive ultra-low power consumption levels, with a deep sleep suspend of 50 µW or less.

The i.MX 7ULP offers Rich OS support (Linux, Android), as well as sophisticated Real-Time Operating Software (RTOS) support (FreeRTOS), and additional features suitable for IoT or any portable use case that demands long battery life.

The i.MX 7ULP family of processors is faster when required and more energy-efficient when performance is not as critical, enabling dynamic trade-offs. Engineers no longer face a forced selection: low-power processor or high-performance processor. Rather, the selection for performance or power efficiency can be made instantaneously, as needed, without having to reconfigure.

Figure 3: The i.MX 7ULP block diagram. The i.MX 7ULP is extremely flexible, with the ability to dynamically transition from high performance to ultra-low power consumption while maintaining active operation. Bursty performance increases can be applied as needed, to offer the best of both worlds, which is especially relevant to IoT applications. (Image: NXP Semiconductors)

The i.MX 7ULP is well-suited for IoT edge devices, as well as smart home controls, building automation, portable patient monitoring, wearables, and portable scanners. The iMX 7ULP reaches a new level in IoT by offering the high performance required for rendering rich graphical images on a power-sipping wearable.

The IoT bestows upon nearly every industry the promise of significant forward progress by granting access to data at levels heretofore unseen. Harnessing the benefits of knowledge gained through the IoT is not going to be free or arrive without hazard. Yet seeking ever-higher productivity, with the potential to progress from the unknown to the well-informed, and in acquiring a new vehicle with which to spark innovation, we can’t help but proceed.

[1] Note that 1/f noise is found in electronics, music, nature, and other areas, and cannot be filtered out of an analog circuit. Chopper stabilization can be used but introduces switching noise.

Joe Yu is the Vice President and General Manager of the Low-Power MPU & LPC MCU product lines at NXP Semiconductors. He has been in the semiconductor industry since 1988 working for companies including NXP/Philips, Freescale, Toshiba, Altera and Atmel. Yu’s work experience includes applications engineering, marketing, business development as well as general management. His passion is to develop low-power microprocessors and microcontrollers for broad market applications. As greater levels of processing and connectivity push to the edge nodes, one of the key areas of focus he has been championing is to find new ways to reduce the power consumption of these IoT devices.

Yu has a BSEE degree from Santa Clara and resides in Palo Alto, CA.

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