How to Protect ADCs from Input Overvoltage



Any embedded designer falling asleep Rip Van Winkle fashion even just a few years ago would likely find our IoT and wearables world the stuff of science fiction. However, one aspect of this world would be strongly familiar—how crucial it is to protect ADC, the core part of the data acquisition system, for today’s signal chain applications—for applications ranging from Mil-Aero to Industrial to Instrumentation/Wearables or even Medical Instrumentation.

High-performance, fully differential op amps with ultra-low distortion and noise are essential for enabling high-speed, high-performance analog-to-digital converters (ADCs) to achieve high resolution and low total harmonic distortion (THD). The op amp, which we are simply calling a driver here, performs a wide variety of operations at the ADC’s front-end. The driver handles the buffering and amplitude scaling. It converts a single-ended input into a differential output to feed the ADC’s differential input. It adjusts the ADC’s common-mode input signal through voltage setting on its VOCM pin and filters the signal.

In this article we explain how to protect an ADC effectively from input overvoltages caused by an op-amp driver. Use of an 180MHz, low-noise, low-distortion, fully differential ADC driver with a built-in clamp feature to keep the driver output swing within the ADC’s specified supplies is recommended.

This hard clamping protects the ADC from overvoltages on its inputs; no additional external discrete components are needed between this driver and ADC for clamp protection. This design saves both space and cost compared to the traditional approach with protection diodes.

Importance of Protecting ADC from Input Overvoltages

With high-performance ADCs available at a premium price, a system designer must choose a driver that protects the ADC against overvoltages. Today’s 18-bit/20-bit ADCs use a reference voltage/supply voltage of not more than 3.3V, but ADC drivers commonly use either ±5V split supplies or even greater voltages. A negative voltage on the driver VSS pin is used to accommodate the entire ADC rail-to-rail input-signal swing. There is a caveat here. Depending on the input signal to the driver, its output can go well beyond the ADC input supplies. If we do not clamp the driver output voltages to within ADC supply voltages, the ADC can be damaged permanently.

Most ADCs on the market have ESD protection diodes on their inputs to both rails, but those diodes cannot handle currents on the order of > 20mA to 50mA for more than few seconds before becoming permanently damaged. Even leakage through the internal ESD diodes for longer duration can damage the protection diodes and the ADC.

Most designers use either Zener diodes or Schottky diodes on the driver’s outputs to limit input signal swing to the ADC. Four discrete diodes and current-limiting resistors are required in this clamping solution. One example of an alternative is a 180MHz, low-noise, low-distortion, fully differential op-amp driver, the MAX44205, with a built-in clamp that limits its output swing to within the ADC supplies. It thus protects the ADC from overvoltages on the input. The clamping feature of this driver eliminates the four additional discrete components and saves both PCB space and cost.

Implementing Clamping Discretely

Designers use Schottky diodes to clamp the ADC input voltages. This is a good approach as these diodes offer the lowest forward drop voltage of ~0.25V to 0.4V, depending on the current flow through them. There are three other important advantages with the Schottky diodes: 1.) very low reverse-leakage current; 2.) smaller parasitic capacitance; and 3.) very fast reverse recovery time. Of these three benefits with Schottky diodes, the low reverse-leakage current and smaller parasitic capacitance are crucial in precision ADC applications. The third benefit, the fast reverse recovery time, is useful when the diode’s speed into clamping and out of clamping is critical.

Although the parasitic capacitance of Schottky diodes is small, a designer must select a diode with the smallest variation in capacitance with change in the reverse voltage applied to the diode. This nonlinear effect is critical for applications where harmonic distortion is important.

Zener diodes are also used to clamp voltages where crude clamping is required. While operational, Zener diodes have higher reverse-leakage current, thus making them less effective for the ADC applications.

Figure 1 shows the basic way to implement voltage clamping with Schottky diodes for predetermined voltage levels at the ADC input.

figure1
Figure 1. Basic voltage clamping scheme with Schottky diodes.

Figure 1 uses two BAT42 Vishay® Schottky diodes. When the ADC driver outputs go beyond the positive ADC supply, the two Schottky diodes in place on each output to the positive supply voltage start conducting; the diodes maintain both the voltage level of those nodes at 3.3V plus the forward-drop voltage of these diodes. Note that the forward-drop voltage of Schottky diodes varies depending on the power-handling capability of the diodes. Therefore, choose Schottky diodes with a lower forward-drop-voltage specification with a forward-continuous-current specification appropriate for the application.

Of the four resistors, RLIMIT limits current flowing through the Schottky diodes and into the 3.3V rail provided by the voltage regulator. RSERIES protects the ADC’s internal ESD protection diodes. The designer must size these resistors to keep currents at a manageable level for the application.

The RLIMIT resistor also helps to reduce the current sink into the voltage regulator, i.e., 3.3V supply rail. If this current is not limited, the voltage regulator’s output voltage can increase and damage other ICs using the board’s same regulator output supply. If you know that your ADC driver cannot supply more than ~100mA, there is an alternative approach. Do not use current-limiting resistors for the series resistor. An RC anti-aliasing filter between the driver and the ADC will limit the current through external Schottky diodes to manageable levels on the order of ~10mA.

So to repeat, the RLIMIT resistors help to limit the current flow into the 3.3V rail. Moreover, together with the Schottky diode capacitance, they form a lowpass filter and will roll off your circuit bandwidth response. For ADC applications that need higher bandwidth, this is a problem and detrimental to ADC operation.

Protection Circuit Examples

Hard Clamping with External Schottky Diodes
Now we will show a circuit using four Schottky diodes (Figure 2) that protects an ADC from driver output overvoltages. High-performance 16-bit to 20-bit ADCs need a low-noise, low-distortion driver to preserve the quality of the input signal and preserve overall ADC conversion accuracy. Here a pair of 7.5Ω resistors and a 1nF capacitor form an anti-aliasing filter that provides 21.22 MHz cut-off frequency. For brevity, we will not discuss sizing of the lowpass filter components and will limit this article to ADC overvoltage protection alone.

figure2
Figure 2. Clamping driver outputs using four external Schottky diodes protects the ADC from driver output overvoltages.

Figure 2 shows the MAX44206 op amp configured in a gain = 1V/V differential amplifier configuration with ±5V split supplies, VOCM = 1.65V. Each output is DC-level shifted to 1.65V, i.e., midrail of the ADC, to utilize the ADC’s full conversion range from 0V to 3.3V. The ±5V split supply lets the driver provide an output voltage swing over the entire 0V to 3.3V conversion range. The input signal used on the driver inputs is usually equal in amplitude and 180° out of phase to achieve a maximum differential output signal swing. Now that each output is DC-level shifted to 1.65V, each output will have an equal-amplitude signal swing based on the input with 180° phase separation.

In our experiment we performed two test cases:

  1. Output voltage swing on each output set as 3.3VP-P with 1.65VDC bias
  2. Each input is 3.3VP-P with 180° phase separation; the actual differential input voltage (VINDIFF) across the two inputs is 6.6VP-P. Since gain = 1V/V, each output is also 3.3VP-P with 180° phase separation, and a 6.6VP-P differential voltage across the outputs (Figure 3).

    figure3
    Figure 3. The output transient response from the Figure 2 circuit. Here VIN+ = 3.3VP-P and VIN- = VIN+-180°; VOCM =1.65V.

    The Figure 3 oscilloscope plot shows that clamping action has not yet started on each output, because the maximum and minimum voltages on each output are 3.3V and 0V, respectively, as shown on the VOUT curve. Understandably diodes have not turned on yet to protect the ADC.

  3. Output voltage swing on each output set as 5VP-P with 1.65VDC bias
  4. Each input is 5VP-P with a180° phase separation (Figure 4). The actual differential input voltage (VINDIFF) across the two inputs is 10VP-P. Since gain = 1V/V, each output is supposed to be 5VP-P with 180° separation in phase; a 10VP-P differential voltage across the outputs is expected. The 5VP-P with 1.65VDC bias on each output means that the output swings between 4.15V and -0.85V. In reality, as soon as each output goes above 3.3V plus the forward drop voltage of the diode, the diode turns on, starts conducting, and clamps the driver output to 3.92V. Similarly, the diode clamps the driver output to -0.8V.

figure4
Figure 4. Output transient response with hard clamping for the Figure 2 circuit. Here VIN+ = 5VP-P and VIN- = 5VP-P; VIN-= VIN+ -180°; VCLPH = 3.3V; VCLPL = 0V; VOCM = 1.65V.

The supply current consumed during a hard clamp state when the Schottky diodes turn on is on the order of 15mA in the Figure 2 setup. Most ADCs have a 0.3V above and -0.3V below the rails as absolute maximum ratings on their input voltages.

Hard Clamping with No External Discrete Diodes

Now we will show a circuit (Figure 5) that protects an ADC from driver output overvoltages with no external diodes. This solution not only saves PCB space but also the additional cost of Schottky diodes. Figure 5 is almost same as Figure 2 except that the four diodes are absent.
The MAX44205 op amp from Figure 5 has two output clamp pins, VCLPH and VCLPL, available to limit the output voltage levels to predetermined voltages. With the ADC supply rails tied to these clamp pins, driver outputs are clamped to within the ADC rails irrespective of the input swing applied to the driver.

figure5
Figure 5. In this circuit the driver outputs are clamped with no external Schottky diodes or discrete components.

Again, we performed two test cases:

  1. Output voltage swing on each output set as 3.3VP-P with 1.65VDC bias
  2. Again, each input is 3.3VP-P with 180° phase separation (Figure 6). Since gain = 1V/V, each output is also 3.3VP-P with 180° phase separation. In the oscilloscope plot (Figure 6) each output of the driver swings between 3.3V and 0V which is exactly the same as ADC rails and, hence, no clamping action is present so far.

    figure6
    Figure 6. Output transient response for the Figure 5 circuit with VIN+= 3.3VP-P and VIN-= 3.3VP-P; VS+ = +5V; VS- = -5V; VIN-= VIN+ -180°; VOCM = 1.65V.
  3. Output voltage swing on each output set as 5VP-P with 1.65VDC bias
  4. Each input is 5VP-P with 180° phase separation; the actual differential input voltage (VINDIFF) across the two inputs is 10VP-P as shown in Figure 7. Since gain = 1V/V, each output is supposed to be 5VP-P with 180° phase separation. Again, 5VP-P with 1.65VDC bias on each output theoretically means that the output swings between 4.15V and -0.85V. The MAX44205 op amp clamps the output and limit to 3.72V on the positive swing and limit to -0.4V on the negative swing, as shown on the VOUT+ trace (Figure 7).

figure7
Figure 7. The output transient response with hard clamping on the Figure 5 circuit. Here VIN+ = 5VP-P and VIN- = 5VP-P; VS+ = +5V; VS-= -5V; VIN – = VIN+-180°; VOCM = 1.65V.

The MAX44205 op amp has a proprietary clamping mechanism that consumes only 92µA through VCLPL in a hard clamp state. This compares favorably to 10s of milliamps when clamping is done with a discrete design in Figure 4. The output voltage limits for the MAX44205 during clamping are VCLPH + 0.34 and VCLPL – 0.42. Clamping at exactly the supply rails of the ADC is not recommended because the driver output needs to swing to either ADC rail with no distortion. If the driver outputs are clamped at exactly VCLPH and VCLPL, the clamps could turn on when the output is at the ADC supply, thus causing distortion.


headshotSrudeep Patil is an applications engineer working with op amps, comparators, current-sense amplifiers, voltage references, digital potentiometers, and of course, ADCs at Maxim Integrated since July 2011. He resolves customer issues with technical lab support and works on new product launches by performing IC road tests and writing the data sheets along with the application notes. Srudeep has an MSEE with major academic focus on Analog/RF VLSI. Prior to joining Maxim, he worked with NXP Semiconductors as an intern in their analog team working on ADCs and amplifiers.

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