Pentek Introduces Jade Architecture ModuleIdeal for Digital RF Memory Applications and More
- Multi-channel, wide bandwidth, low latency and synchronous XMC module
- Three 200 MHz 16-bit A/D XMC module with multiband digital down converters
- One digital upconverter to two 800 MHz 16-bit D/As · Jade Architecture with Xilinx Kintex Ultrascale FPGA offers price, power and processing performance advantages · Navigator Design Suite expedites development and custom IP integration
Pentek, Inc., today introduced the newest member of the Jade™ family of data converter XMC modules. The Model 71821 is a three-channel, 200 MHz, 16-bit A/D, with multiband digital down converters (DDCs) and one digital upconverter (DUC) to two 800 MHz 16-bit D/As, XMC module based on the Xilinx Kintex Ultrascale FPGA and can be used in many high-performance applications.
The Model 71821 is ideal for engineers building a Digital RF Memory (DRFM) application where multi-channel inputs can digitize an incoming RF input signal at bandwidths up to 80 MHz and then generate a processed version of that RF signal as an analog output with very low and deterministic latency.
For DRFM radar applications, an incoming radar pulse is digitized and sent to the FPGA, which can apply a range of DSP algorithms before delivering the modified signal to the D/A for transmission back to the radar to simulate a reflected pulse. These algorithms are intended to confuse, deceive, or disable the radar, depending on mission objectives. Being a coherent representation of the original signal, the transmitting radar will not be able to distinguish it from other legitimate signals it receives and processes as targets. If the signal is stored in memory, it can be used to create false range targets both behind (reactive jamming) and ahead of (predictive jamming) the target intended for protection. Slight modifications in frequency simulate Doppler shifts to create false target velocity. DRFM can also be used to create distorted phase-fronts, which is essential for countering monopulse radar angular measurement techniques.
“Our military, defense and aerospace customers can now take advantage of the Jade Architecture and our Navigator Design Suite,” said Bob Sgandurra, director of Product Management of Pentek. “Access to over 90 Pentek IP modules with industry-standard AXI4 interfaces reduces development costs and time through graphical design entry and high-level point-and-click interconnects.”
A/D Converter Stage: The front end accepts three analog HF or IF inputs on front panel SSMC connectors with transformer-coupling into three Texas Instruments ADS5485 200 MHz, 16-bit A/D converters. The digital outputs are delivered into the Kintex UltraScale FPGA for signal-processing, data capture and routing to other module resources.
Digital Upconverter and D/A Stage: A TI DAC5688 DUC (digital upconverter) and D/A accepts a baseband real or complex data stream from the FPGA and provides that input to the upconvert, interpolate and dual D/A stages.
Clocking and Synchronization: Two internal timing buses provide either a single clock or two different clock rates to the A/D and D/A signal paths.
Performance IP Cores
A/D Acquisition IP Modules: The Model 71821 features three A/D Acquisition IP modules for easily capturing and moving data. Each IP module can receive data from any of the three A/Ds or a test signal generator. Powerful linked-list DMA engines move the A/D data through the PCIe interface in a unique Acquisition Gate Driven mode. In this mode, the length of a transfer performed by a link definition need not be known prior to data acquisition; rather, it is governed by the length of the acquisition gate. This is extremely useful in applications where an external gate drives acquisition and the exact length of that gate is not known or is likely to vary. Within each A/D Acquisition IP Module is a powerful DDC IP core. Because of the flexible input routing of the A/D Acquisition IP Modules, many different configurations can be achieved including one A/D driving both DDCs or each of the two A/Ds driving its own DDC.
D/A Waveform Playback IP module: The Model 71821 factory-installed functions include a sophisticated D/A Waveform Playback IP module. A linked-list controller allows users to easily generate waveforms stored in either on-board memory or host memory for both D/As. Parameters including length of waveform, delay from playback trigger, waveform repetition, etc. can be programmed for each waveform. Up to 64 individual link entries can be chained together to create complex waveforms with a minimum of programming.
The Jade Architecture
The Pentek Jade architecture is based on the Xilinx Kintex UltraScale FPGA, which raises the digital signal processing (DSP) performance by over 50% with equally impressive reductions in cost, power dissipation and weight. As the central feature of the Jade architecture, the FPGA has access to all data and control paths, enabling factory-installed functions including data multiplexing, channel selection, data packing, gating, triggering and memory control. A 5 GB bank of DDR4 SDRAM is available for custom applications. The memory to Gen.3 x8 PCIe link can sustain 6.4 GB/s data transfers. Eight additional gigabit serial lanes and LVDS general purpose I/O lines are available for custom solutions.
Navigator Design Suite for Streamlined IP Development Pentek’s Navigator™ Design Suite was designed from the ground up to work with Pentek’s Jade architecture and Xilinx’s Vivado Design Suite® providing an unparalleled plug-and-play solution to the complex task of IP and control software creation and compatibility. Graphical design entry for Xilinx and Pentek AXI4-compliant IP modules using the Xilinx IP Integrator greatly speeds development tasks. The Navigator Design Suite consists of two components: Navigator FDK (FPGA Design Kit) for integrating custom IP into Pentek sourced designs and Navigator BSP (Board Support Package) for creating host applications. Users can work efficiently at the API level for software development and with an intuitive graphical interface for IP design. The Navigator BSP is available for Windows and Linux operating systems.
Pre-Configured SPARK System Ready for Immediate Use With a Pentek 8266 SPARK® PC, 8264 SPARK 6U VPX, or 8267 SPARK 3U VPX development system, work can begin immediately on applications. A SPARK system saves engineers time and expense associated with building and testing a development system and ensures optimum performance of Pentek boards. SPARK development systems are ready for immediate operation with software and hardware installed. In many applications, the SPARK development system can become the final deployed application platform.
The Model 71821 XMC module is designed to operate with the wide range of carrier boards in PCIe, 3U & 6U VPX, AMC, and 3U & 6U CompactPCI form factors, with versions for both commercial and rugged environments.