Timing Closure for Mil/Aero Designs

Getting to the next level of performance requires optimization on all fronts—the architectural design, code, and tools.

Military and aerospace engineers need to work with ever-increasing demands on latency, bandwidth, and extreme temperatures to meet exacting application requirements and bring the project in on schedule.

Capturing a design in a concise and succinct manner by working at a higher level of abstraction means fewer errors and easier debugging. However, this approach typically yields performance trade-off concerns. Achieving high performance in a highly complex field programmable gate array (FPGA) design requires manual optimization of register transfer level (RTL) code, not possible for generated RTL code from a C-to-RTL development environment.

Another mil/aero application that benefits from the use of timing closure tools is software-defined radio (SDR).

Solutions are available that can minimize trade-off by optimizing the design itself using FPGA tool settings to identify the best combination of synthesis and place-&-route settings using machine learning and placement exploration. Engineers  gain a way to push the performance envelope without sacrificing productivity and changes to the workflow.

(U.S. Air Force photo/Naoto Anazawa)

Finding the Right FPGA Tool Settings
Although engineers are aware of the existence of FPGA tool settings, these settings are often underutilized. Usually, they are used only when a design doesn’t meet time closure. Even for designs that meet their performance targets, the potential for an additional 10 to 50 percent performance improvement exists.

The challenge is selecting the right tool settings since different FPGA tools present anywhere from 30 to 70 settings for synthesis and place & route. With so many combinations, it’s confusing. Fortunately, tools exist that can manage and run design exploration in an automated and disciplined way.

The last challenge is insufficient compute power. Typical embedded applications are designed on a single computer, and running multiple compilations requires more compute power, forcing a trade-off with time. If more compilations can be run concurrently, the turnaround time will be shorter.

Optimizing High-Level Design
Tools designed to minimize trade-off and increase timing performance up to 50% without any change in the RTL code are commercially available. The effects of design exploration are best explained with an illustration of a design commonly used in video processing that does a Sobel Filter Implementation (Figure 1). The reference design targets an FPGA with a dual Arm® Cortex®-A9 MPCore™.

Figure 1: The design shows the effects of design exploration for Sobel Filter Implementation used in video processing.

The design has a clock period of 5.00ns or 200 megahertz (MHz). According to timing estimates, it misses timing by 506ps, which translates to 181MHz or 10% short of its target speed (Figure 2).

Figure 2: A timing report analyzes the timing estimates and determines the design misses the target.

Without changing the C++ code, the engineer exports the design into RTL code. Using a design exploration tool, the engineer opens the project (xpr) and optimizes the design by running multiple compilations concurrently with different FPGA tool settings.

Figure 3: The design met performance targets and closure using tool settings.

After two rounds of optimizations with a total of 15 compilations, the design met its performance target of 200MHz, achieved without changes to the source code (Figure 3).

Design Exploration on RTL Projects
This example doesn’t mean that gains can only be obtained from designs created in higher level designs.

Performance gains are possible on projects created with RTL code. Another mil/aero application that benefits from the use of timing closure tools is software-defined radio (SDR). In this example, a reference design is created directly with RTL code. It is a high-performance, highly integrated radio frequency (RF) Agile Transceiver™ designed for use in 3G and 4G base station applications. The device combines an RF front end with a flexible mixed-signal baseband section and integrated frequency synthesizers as well as a configurable digital interface to a processor.

The original clock period is 4ns or 250MHz and reference design meets timing by default. To make the design fail timing, engineers set an aggressive clock period of 2 nanoseconds and the new target speed of 500MHz. Under the new conditions, it fails timing by 246ps and runs at 445 MHz.

Using the same conditions where the RTL code is untouched, the design is optimized by exploring various FPGA tool settings undergoing three rounds of optimization comprising 60 compilations.

Figure 4: Optimized results from the SDR design show substantial improvement.

Results show that the final worst negative slack improved by 79.2% from -246ps to -0.051ps as compared to the original worst slack, equivalent to a clock speed of 487MHz and a 9.4% FMax improvement (Figure 4).

Next Level of Performance
Inevitably, military and aerospace design and electronic devices will become more complex to meet increasing demands. Newer FPGA software technologies and methodologies will be embraced to keep up with quality, productivity, and demand. While the potential of FPGA design tools is less understood, tool setting exploration can overcome performance trade-offs for higher-level designs, thus retaining productivity benefits. Engineers will become more adept at using the tool setting exploration options of FPGA design tools that have recently  become available to meet rigorous mil/aero design challenges.

Kirvy Teo is a Plunify co-founder and chief operating officer. He has more than 15 years of experience in design and building complex software systems. Before starting Plunify, he founded a company providing text messaging products and services in the early days of the mobile industry. He graduated from the National University of Singapore with a Bachelor of Science degree in Computer Science.


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