Magma IC Implementation Software Integrated into TSMC Reference Flow 7.0



Magma and TSMC to address variability, power and design for manufacturability


SANTA CLARA, Calif., and HSINCHU, Taiwan, July 18, 2006 — Magma® Design
Automation Inc. (Nasdaq: LAVA), a provider of semiconductor design software, and Taiwan
Semiconductor Manufacturing Company (NYSE: TSM) today announced the integration of Magma’s software into TSMC’s Reference Flow 7.0. Magma’s integrated circuit (IC) implementation system, including Blast Create™, Blast Fusion®, Blast Power™, Quartz™
SSTA, Blast Yield™ TX and Quartz DRC, enables users to address the design challenges and variability that emerge in 65-nanometer (nm) process geometries. With this flow
designers can achieve better timing, area and power, more robust designs, higher yields
and faster time to production silicon.

The Magma software’s inclusion in the TSMC Reference Flow 7.0 caps years of
collaboration between the two companies, the goal of which has been to offer designers
effective and reliable design and manufacturing capabilities for their critical ICs. As a
result, TSMC has included statistical static timing analysis (SSTA) as well as advanced
low-power and design for manufacturability (DFM) methodologies in Reference Flow 7.0.

“We’ve worked very closely with Magma to model variability at 65-nm and below, and to
anticipate the challenges designers face,” said Ed Wan, senior director of design service
marketing at TSMC. “With Magma software in the TSMC Reference Flow 7.0, designers can
access a comprehensive and integrated implementation and verification flow that accounts
for the complexities and interdependencies of power, timing, area and variability.”

“Although we’ve been working with TSMC for years, having a complete methodology
integrated into the TSMC Reference Flow 7.0 is a milestone in our drive to become one of
the top electronic design automation providers,” said Kam Kittrell, general manager of
Magma’s Design Implementation Business Unit. “TSMC’s inclusion of our software in
Reference Flow 7.0 gives designers additional confidence in their ability to achieve
silicon success.”

TSMC Reference Flow 7.0

The release of Reference Flow 7.0 continues TSMC’s tradition of providing proven design
methodologies and recommended tools to enable silicon success in advanced process
technologies. This design support ecosystem lowers the risk of migrating to 65-nm
technology. Reference Flow 7.0 specifically addresses advanced power management
techniques, statistical static timing analysis and design for manufacturability. This is
the first TSMC reference flow to include the complete Magma methodology.

Blast Create, Blast Fusion – Enabling Intelligent Timing, Area and Power Tradeoffs
Magma provides a complete RTL-to-GDSII flow within a single executable. Blast Create and
Blast Fusion are the cornerstones of the integrated flow. Blast Create is an
RTL-to-placed-gates system that enables logic designers to synthesize, visualize, evaluate
and improve the quality of their RTL code, design constraints, testability requirements
and floorplan. Blast Create integrates fast, full-featured, high-capacity logic and
physical synthesis capabilities, full and incremental static timing analysis, design for
test (DFT) analysis and synthesis, and power analysis. Blast Fusion is a physical design
solution that includes optimization, place and route, useful skew clock generation,
floorplanning and power planning, RC extraction and a single, built-in incremental timing
analyzer. Based on Magma’s unified data model, Blast Fusion accurately predicts final
timing prior to detailed placement, eliminates timing closure iterations and enables rapid
design closure, taking into account new nanometer design challenges such as on-chip
variation (OCV). Blast Fusion fully supports TSMC’s 65-nm routing rules.

Blast Power, Blast Rail – Advanced Power Management

With Blast Power and Blast Rail™ in the TSMC Reference Flow 7.0, designers have a
comprehensive RTL-to-GDSII solution for power optimization and management. In this system,
low-power analysis and optimization engines are integrated with – and applied
throughout – the entire RTL-to-GDSII flow. Advanced capabilities are provided for
power grid synthesis, multi-Vt and multi-VDD support, IR Drop analysis and automatic
decoupling capacitor insertion, and static and dynamic power optimization. Magma’s
methodology also supports insertion and sizing of different types of MTCMOS switches such
as global header/footer switches, distributed or fine grain header/footer switches and
standard-cell-based switches.

Quartz SSTA – Managing Process Variation

At 65-nm, the traditional use of multiple process corners and design margins to combat
process variation significantly compromises performance and leads to pessimistic designs.
To help customers reduce the time and effort required to close timing and ensure robust
designs, TSMC has included Magma’s Quartz SSTA in Reference Flow 7.0. Quartz SSTA allows
designers to manage process variation throughout the RTL-to-GDSII flow by identifying and
fixing critical paths that are sensitive to process variation. The result is a more robust
design with improved yield across the full process window and environmental conditions.

Blast Yield TX, Quartz DRC– Improving Yields, Reducing Costs
Blast Yield TX addresses design for manufacturability within the implementation flow
eliminating costly iterations associated with post-layout DFM fixing. Magma’s DFM solution
combines both rule- and model-based analysis, providing silicon accuracy without incurring
large run-time penalties. DFM hot spots are eliminated without introducing DRC violations
or affecting critical timing. Blast Yield TX and the lithography modeling option within
Quartz DRC are qualified by TSMC. Blast Yield TX integrates the TSMC virtual
chemical-mechanical polishing (VCMP) simulator, TSMC-correlated critical-area analysis
(CAA) and the lithography process check (LPC) capabilities of Quartz™ DRC into the
Magma Blast Fusion flow. With Blast Yield TX and Quartz DRC, designers have a complete DFM
solution for minimizing random and systematic yield loss.

About TSMC

TSMC is the world’s largest dedicated semiconductor foundry, providing the industry’s leading process technology and the foundry’s largest portfolio of process-proven library, IP, design tools and reference flows. The company operates two advanced 12-inch wafer fabs, five 8-inch fabs and one 6-inch wafer fab. TSMC also has substantial capacity commitments at its wholly owned subsidiaries, WaferTech and TSMC (Shanghai), and its joint venture fab, SSMC. TSMC is the first foundry to provide 65-nm production capabilities. Its corporate headquarters are in Hsinchu, Taiwan. For more information about TSMC please see http://www.tsmc.com.

About Magma

Magma’s software for integrated circuit (IC) design is recognized as embodying the best in semiconductor technology. The world’s top chip companies use Magma’s EDA software to design and verify complex, high-performance ICs for communications, computing, consumer electronics and networking applications, while at the same time reducing design time and costs. Magma provides software for IC implementation, analysis, physical verification, characterization and programmable logic design, and the company’s integrated RTL-to-GDSII design flow offers “The Fastest Path from RTL to Silicon”™. Magma is headquartered in Santa Clara, Calif. with offices around the world. Magma’s stock trades on Nasdaq under the ticker symbol LAVA. Visit Magma Design Automation on the Web at www.magma-da.com.

Contact Information

Magma Design Automation Inc.

1650 Technology Drive
San Jose, CA, 95110
USA

tele: 408.565.7500
fax: 408.565.7501
ipsupport@magma-da.com
www.magma-da.com

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