New White Papers
Cavium’s New OCTEON III family of processors feature latest Imagination Technologies MIPSr5 architecture
Imagination Technologies (IMG.L), a leading multimedia, processor, communications and cloud technologies company, today announced that long-time MIPS licensee Cavium, Inc. (NASDAQ:
In wireless, wireline and financial “big data” applications, moving all those packets needs...
When designing a system on a chip (SoC) that employs one or more embedded processor cores, the choice...
While the main manufacturing flows are still focusing on optical lithography, eBeam and EUV are still...
#CHIPS: "China's MilkyWay-2 Retakes Supercomputer Crown" / (NextGenLog)
Powered exclusively by Intel Xeon and Xeon Phi parallel processors, China's MilkyWay-2 supercomputer was declared the world's fastest by the Top500.org twice yearly listing: R. Colin Johnson @NextGenLog Further Reading...
An online retailer priced the forthcoming chips between $500 and $1,000 before removing them from its site. Would AMD really charge that much for its top-performing CPUs?...
Blog Post: The Mango Meter! / (TI E2E Community)
C.P. Ravikumar, Texas Instruments The date for submission of proposals for Texas Instruments Innovation Challenge: India Analog Design Contest is approaching! Are you looking for project ideas for the contest? Here is an idea that may lead to .. err.. some “fruitful” R&D! Summer is the season for mangoes....
Linux has its own built-in hypervisor, KVM, for x86 virtualization, and now IBM is porting it to its Power architecture....
From small to large, PICMG evolves COM Express, CompactPCI, AdvancedTCA and MicroTCA.
Multiprocessing is at the heart of high-performance embedded computing—and new technologies enable it to deliver significantly improved performance.
Offloading performance or power critical functions from a merchant processor into a hardware accelerator is commonplace in today’s SoC designs. Such accelerators are “specialized
Monolithic AMD embedded G Series SoCs combine x86 multicore, Radeon graphics and a Southbridge. It’s one-stop-shopping, and it’s a flood targeting Intel again.
Are four cores really better than two for smartphones? Smartphones and tablets are migrating towards new and faster application processors, basebands, graphics chips and memories.
Flash memories wear out, but there are ways to minimize their demise, from application changes to file system software.
The OpenCL language and ecosystem could be a lot more portable than it is today. The idea of a static OpenCL runtime coupled with an OpenCL-to-C translator would make OpenCL code theoretically runnable anywhere C and C++ can be compiled for.
IP giant also talks about Intel, finFETs and the cloud Needless to say, ARM Holdings is the dominate supplier of processor intellectual property (IP) in the booming cell-phone
An exclusive interview on the manufacturing and design issues Intel is wrestling with at advanced nodes—and just how far the road map now extends. Editor’s Note: This exclusive
To adequately address cloud computing requirements means new hardware, new infrastructure, new software... and sometimes even new business models are needed. It’s a “Gigantic Data” dilemma best solved using Intel’s latest solutions.
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CriticalBlue raises the core performance, capacity, and responsiveness of many Android and Linux products running on ARM, x86, and Power platforms. We bring deep knowledge of how to optimize Android and Linux software stacks for best performance on your mobile and embedded platforms. CriticalBlue's internally developed tool suite, Prism, gives developers unique insight into multicore hw/sw performance issues, their root causes, and their most effective solutions, as we demonstrate in several case studies. To solve mobile Android and Embedded Linux product performance challenges, contact CriticalBlue to truly launch fast and stay ahead.
Debugging Heterogeneous Multicore System based on TI OMAP-L138 with Enea Optima Development Tools. Hosted by Mattias Bertilsson, Director of Product Management at Enea.
Sean Koehl from Intel Labs shows how future computers powered by multi-core processors will be able to bring amazing 3-D visuals and the ability to intelligently manage digital media, allowing you to record and view just the highlights you want to see.
Interview by John Blyler with Max Domeika from Intel
Featured White Papers
Distributed systems range from simple multi-threaded applications to multi-slot chassis-based systems to networked clusters of servers. Topologies get more complex when these systems move into cloud-based environments, and more diverse when they involve machine-to-machine (or M2M) solutions. Providers of distributed system software solutions face a number of challenges in building, debugging and maintaining a set of connected applications. Managing these systems requires powerful modeling and a variety of management interfaces to meet a diverse set of needs. The services provided by a distributed system often require a high level of availability. The middleware frameworks that make up Enea Element address many of these challenges.
Traditional high-performance computing platforms are limited by the connection bandwidth and latency between the multiple computing elements needed to achieve the performance targets. For the embedded market, the difficulty is compounded by the demanding environmental requirements. The VPX standard resolves this limitation with a large number of high-throughput point-to-point connections between the processing elements in a rugged mechanical structure.
OpenVPX System Bandwidth: A comparison of 10Gb Ethernet Performance, Serial Rapid IO, and InfiniBand
This paper compares the bandwidth available to two common types of dataflow for systems based on the VITA 65 CEN16 central switched topology, using three different fabrics – Serial RapidIO (SRIO), 10 Gigabit Ethernet (10GbE), and Double Data Rate InfiniBand (DDR IB).
A CGL compliant, high performance, high availability carrier grade Linux designed for next generation multi-core network architectures.…
This white paper takes a fresh look at the performance of low-power x86 CPUs, now that VIA has introduced dual-core and quad-core CPUs.
Market demand continues to grow for high-performance imaging, communications and security systems. Solutions need to contain scalable power-efficient processors with better integrated graphics capabilities than ever before. From imaging to communications to security to raw scalar throughput, the second generation Intel® Core™ processors (formerly codenamed Sandy Bridge) combining with C206, Q67 and QM67 chipsets offer either a simple, power-efficient upgrade or a massive architectural simplification.
At the Consumer Electronics Show (CES) on January 7, 2010, Intel® announced 27 new processors in its Core® i3, Core® i5 and Core® i7 families. Significantly for the embedded industry, twelve of these were targeted specifically at embedded applications. Early indications are that the Core i7 will offer either more processing performance per watt compared with earlier products (estimated at around 20%), or lower power consumption per unit of processing performance than its predecessors.