Embedded Hypervisor for Freescale QorIQ™ P4 Series Communications Platforms Supports Virtualization and Partitioning

Freescale’s QorIQ multicore communications platforms, built using high-performance e500mc cores based on Power Architecture ® technology, are the next-generation evolution of the popular PowerQUICC® communications processors.

The QorIQ P4080 eight-core processor is the first product offered in the QorIQ P4 platform series. The e500mc cores, developed specifically for QorIQ multicore platforms feature a new embedded hypervisor architecture. This architecture facilitates the development of efficient hypervisor software which in turn enables the creation of systems where multiple partitions can safely and securely coexist. System resources such as processor cores, memory and I/O devices can be partitioned or shared. In a partitioned system, each partition can independently run an individual operating system.

The e500mc embedded hypervisor architecture introduces several changes from previous generations of the e500 family of CPUs:

  • Guest state is a third privilege level in the e500mc embedded hypervisor. When the hypervisor is hosting an OS, it runs in hypervisor state, and the hosted OS and its applications run in guest state
  • Interrupts may be selectively directed to the guest state without any involvement by hypervisor software
  • The e500mc MMU features an extended virtual address space which enables hypervisor software to efficiently manage multiple partitions.

The QorIQ P4080 also features a new peripheral access memory management unit (PAMU) that provides I/O device-to-memory access control, protection and address translation. This is an essential component in enforcing security between partitions and would typically be managed by the hypervisor software.

An OS that was originally programmed to run on an existing e500 family CPU can continue to run with few modifications on an e500mc which has implemented the embedded hypervisor features. This allows ISVs to continue providing systems software in the same environment that existed before the embedded hypervisor was introduced. In addition, the Freescale-developed hypervisor presents a virtual machine very close to the actual underlying hardware, allowing operating systems to be implemented so that they can run under the control of a hypervisor or on bare-metal with few, if any, changes.

Embedded Hypervisor Software

Freescale offers hypervisor software that enables the efficient and secure partitioning of a multicore system.

Key features of the Freescale embedded hypervisor software architecture include:

  • Partitioning of CPUs, memory and I/O devices, where each partition is assigned one or more CPU cores and each has a private memory region
  • Complete partition isolation so that one partition cannot access the private resources of another
  • Mechanisms to selectively enable partitions to share certain hardware resources, such as memory
  • Virtualization support for mechanisms that enable partitions to share certain devices, such as the system interrupt controller
  • Security and isolation with very low overhead
  • A combination of full emulation and para-virtualization to maintain high performance while minimizing guest OS changes when migrating code from an e500mc CPU to the embedded hypervisor.

The hypervisor provides services to guest software through emulation and hypercalls (or hcalls). Emulation is when normal CPU instructions and registers are used to provide a service where the guest software is unaware that it is running under a hypervisor. Hypercalls provide a mechanism by which the hypervisor presents an API to guest software for various services.

Virtual CPU

The guest software running under the control of a hypervisor-created partition that sees a set of Power Architecture instructions and registers that is like an e500mc CPU but with some resources removed. Standard e500mc CPU features can be used without changing guest software, however, in order to provide the same programming model between the guest and the CPU for supervisor-level code, the hypervisor emulates some instructions and registers.

I/O and Interrupts

External interrupts are received directly by partitions and can be handled by guest software with no added latency introduced by the hypervisor. The processor provides an External Proxy Register (EPR) designed to enable guest interrupt handlers to read the interrupt vector for an external interrupt without requiring an access to the interrupt controller. A virtual MPIC is provided through an hcall interface to provide interrupt controller services.

Partition Management Services

The Freescale embedded hypervisor software provides mechanisms that enable one partition to use hcalls to manage other partitions. A manager partition can load images into, start, and stop a managed partition.

Byte-channel Services

In addition, the hypervisor supports an hcall-based service called a bytechannel that provides an interrupt-driven character-based I/O channel. Each byte-channel has an endpoint, and a flexible set of endpoints are supported. The byte-channel to UART multiplexer provides the capability to multiplex a number of byte-channel streams over a physical UART to a host system. The host system runs a mux server that de-multiplexes the streams and makes them available through network ports.

Other Hypervisor Services

Additional hcall-based services include:

  • Inter-partition doorbell services that enable one partition to interrupt another partition
  • GPIO services that enable the partitioning and assignment of individual general purpose I/O pins to partitions
  • Power management services that enable partitions to access the power-saving and management capabilities of the QorIQ communications processor

ePAPR Boot Architecture

The embedded hypervisor adopts the Power.org ePAPR (Embedded Power Architecture Platform Requirements) architecture that defines two aspects of how operating systems are booted: device trees and multi-CPU boot.

A device tree is a data structure passed to a guest OS at boot that defines the physical and virtual resources that make up the partition. The multi-CPU boot architecture defines mechanisms on how secondary CPUs are released.

For more information on QorIQ multicore communications platforms, including the full version of this white paper, please visit www.freescale.com/qoriq.

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