The UltraSPARC® T2 Processor



Multicore and multithreaded processor with integrated networking and cryptography

Highlights

  • Chip multithreading (CMT) technology for massive throughput
  • Integrated cryptographic acceleration and 10 Gigabit Ethernet (GbE) enables secure computing at wire speed
  • Integrated networking reduces board space, power, and system cost
  • Scalable, multithreaded solution enables equipment suppliers to deliver software-based upgrades to improve time to market
  • Designed with virtualization in mind to provide hardware-based domain protection

Overview

The UltraSPARC T2 processor is a highly integrated multicore and multithreaded system on a chip (SoC) processor featuring Sun’s unique chip multithreading technology. Because speeds of traditional processors have increased much faster than the memory speed, traditional processors spend a significant amount of time waiting for data from memory.

The UltraSPARC T2 processor incorporates four, six, or eight independent 64-bit SPARC® cores, with each core having full hardware support for execution of eight independent threads. A thread can be a process that is part of a parallel program, or a program by itself. Each SPARC processor core consists of two integer execution units, a floating-point and graphics The processor cores communicate to the L2 cache through a nonblocking crossbar switch. The crossbar connects the eight SPARC processor cores to the eight banks of the L2 cache and the I/O port. The L2 cache connects to four on-chip DRAM controllers, which interface directly with a pair of fully buffered (FB-DIMM) channels.

Each core integrates 16 KB, eight-way associative instruction Level 1 cache (L1) with 8 KB, four-way associative Level 1 data cache. The eight SPARC processor cores share an eight-banked, 4 MB Level 2 cache (L2). Each bank of the L2 cache is 16-way set associative with a line size of 64 bytes. The eight banks of L2 cache enable eight simultaneous accesses to support the high bandwidth requirements of the UltraSPARC T2 processor.

The UltraSPARC T2 processor incorporates up to eight, independent 64-bit SPARC® cores, with each core having full hardware support for execution of eight independent threads.

The processor cores communicate to the L2 cache through a nonblocking crossbar switch. The crossbar connects the eight SPARC processor cores to the eight banks of the L2 cache and the I/O port. The L2 cache connects to four on-chip DRAM controllers, which interface directly with a pair of fully buffered (FB-DIMM) channels.

In addition, the SoC includes an on-chip PCI Express (PCIe) controller and two native 1 Gigabit and 10 Gigabit Ethernet (GbE) media access controllers (MACs). The PCIe implements PCI Express Base Specification 1.0a and supports x1, x4, and x8 configurations. The network interface unit (NIU) implements two on-chip 10 GbE ports with XAUI interfaces. The PCIe and XAUI interfaces are programmable to drive short and long distances to traverse a backplane for blade applications.

The high level of system integration on the UltraSPARC T2 processor reduces overall system complexity, component count, and power consumption. The UltraSPARC T2 processor combines the benefits of general-purpose processing and flexible programming, along with the scalability of chip multithreading. This offers the ability to efficiently consolidate Control Plane and Data Plane operations — as well as security functions — on a single chip.

SPARC® core

  • SPARC V9-compliant CMT with eight threads/core at 1.0 GHz and 1.2 GHz
  • The eight threads share instruction and data caches and are divided into two groups per core
  • Up to two instructions can issue per cycle, one per thread group
  • The UltraSPARC T2 processor’s fine-grained multithreading scheme minimizes throughput performance losses arising from branch miss predictions and cache misses
  • Two integer execution pipelines/core
  • Fully pipelined floating-point/graphics unit
  • Stream processing unit for crypto-graphic acceleration
  • Cache
  • L1 caches and the translation lookaside buffers (TLBs) are shared by all eight threads
  • L1 instruction cache size: 16 KB
  • L1 data cache size: 8 KB
  • L2 cache size: 4 MB, eight-way banked with a set associativity of 16 in order to meet the bandwidth demands of eight cores, each having eight threads per core
  • Full L2 cache coherency— any processor— any bank

Memory controller

  • Four on-chip memory controllers
  • Dual-channel FB-DIMM ports are associated with the adjacent pair of L2 banks
  • 10-bit southbound and 14-bit northbound FB-DIMM channel protocols
  • Supports 256 Mb, 512 Mb, 1 Gb, and 2 Gb DRAM components
  • Supports 128 bits of write data and 16 bits ECC per SDRAM cycle, and 256 bits of read data and 32 bits ECC per SDRAM cycle
  • ECC generation, check, correction

Advanced crypto/security engine

  • Full duplex encryption/decryption
  • Supports bulk encryption, authentication operations, and publickey cryptography
  • High-speed crypto engine per core supporting RC4, DES/3DES, AES (128-, 192-, and 256-bit key lengths), AES-GCM
  • AES modes of operation supported: ECB, CBC, and CTR
  • DES modes of operation supported: ECB, CBC, and CFB
  • MD5, SHA-1, SHA-256 authentication functions including keyed hashing (HMACs)
  • Key exchange, key generation, and authentication acceleration for security protocols such as IPsec and SSL/TLS
  • Provides direct hardware support for RSA, DSA, and Diffie-Hellman operations for up to 2,048 bit keys via modular exponentiation
  • Supports key exchange and signature generation and verification using elliptic curve cryptography
  • Additional cypher support available on a per-thread basis; contact factory for details

Network interface unit

  • Two 10 Gb/sec line interfaces
  • Two XAUI interfaces
  • Packet distribution and order sequencing in hardware
  • Line rate packet classification based on layer 1/2/3/4 protocol stack
  • Multiple DMA engines with DMA port binding
  • Hardware virtualization support

10 GbE MAC

  • Two dual-speed, full-duplex MACs (1 Gb/10 Gb)
    – 16 unique MAC addresses per port
    – Jumbo frame support to 9,216 bytes
    – PAUSE frame support per IEEE 802.3
    – Optional PAUSE generation via control registers
    – Option for buffering of entire egress packets before transmitting them to the line port, enabling discard of errored packets before transmission
  • Store-and-forward operation
  • Error checking
    – Frame integrity and frame length checks
    – CRC checking/generation and optional bypass mode
    – Option for discard of packets with CRC errors in receive direction
  • Remote/local fault signaling at reconciliation sublayer (RS)
  • Automatic padding of transmitted packets of less than minimum frame size
  • Support for big-endian data formats
  • Programmable inter-frame gap (IFG)
  • Capable of variable idle insertion to upport WAN interconnect sublayer (WIS) data pacing

PCI Express interface unit

  • Operates at 2.5 GHz per lane per direction, differential signals with variable output levels to optimize for long- or short-reach interfaces
  • Implements the root complex behavior of the PCI Express Base Specification 1.0a
  • Implements the transaction layer, data link layer, and logical subblock of the physical layer
  • Supports x1, x4, and x8 configurations at the data rate of 2.5 Gb/sec
  • Supports lane reversal

Test and diagnostic support

  • IEEE 1149.1 port with memory BIST, scan, and JTAG boundary scan

Standards compliance

    IEEE 802.3-2005
    IEEE 802.1q for VLAN support
    IEEE 802.3x for flow control and PAUSE frame generation
    IEEE 802.3ae-2005 for 10 GbE MAC

Typical applications

  • Application delivery systems
  • Intrusion detection systems
  • Multiservice Ethernet switches
  • Routers
  • Security appliances
  • Video streaming and IPTV
  • WAN optimization
  • Wireless LAN controllers
  • Wireless Control Plane and Data Plane processors for CDMA, UMTS, WiMax, and LTE


Contact Information

Sun Microsystems, Inc.

4150 Network Circle
Santa Clara, CA, 95054
USA

tele: 650.960.1300
fax: 800.555.9SUN
www.sun.com

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