QorIQ™ Communications Platforms P4 Series

QorIQ P4080 Multicore Processor:

The QorIQ P4080 multicore processor, the first product offered in the QorIQ P4 platform series, delivers industry-leading performance in the under 30-watt power category. It combines eight Power Architecture® e500mc cores operating at frequencies up to 1.5 GHz with high-performance datapath acceleration logic, as well as networking I/O and other peripheral bus interfaces.

The P4080, built in 45 nm technology, is designed to deliver high-performance, next-generation networking services in a very low power envelope.

The QorIQ P4080 processor is designed for combined control and dataplane processing, enabling high-performance Layers 2-7 processing. Its high level of integration offers significant performance benefits compared to multiple discrete devices, while also greatly simplifying board design. The processor is well-suited for applications that are highly compute-intensive, I/O intensive or both.

FEATURES & BENEFIT

• Ground-breaking three-tiered cache hierarchy
  • Each core has an integrated Level 1 cache as well as a dedicated Level 2 backside cache, to improve performance
  • Multi-megabyte Level 3 cache for those tasks for which a shared cache is desirable

• CoreNet™ coherency fabric to manage full coherency of the caches and provide scalable on-chip, point-to-point connectivity supporting concurrent traffic to and from multiple resources connected to the fabric, eliminating single-point bottlenecks for non-competing resources
• e500mc cores leverage advanced virtualization technology work as eight symmetric multiprocessing (SMP) cores or eight completely asymmetric multiprocessing (AMP) cores
• Full processor independence via an embedded hypervisor, including the ability to independently boot and reset each e500mc core
• Cores can run different operating systems (OSes) or run OS-less

TECHNICAL SPECS

• Eight high-performance Power Architecture e500mc cores, each with a 32 KB instruction and data L1 cache and a private 128 KB L2 cache
• 2 MB shared L3 CoreNet platform cache
• Hierarchical interconnect fabric
  • CoreNet fabric supporting coherent and non-coherent transactions with prioritization and bandwidth allocation amongst CoreNet end-points; 800 Gbps coherent read bandwidth; queue manager fabric supporting packetlevel queue management and QoS scheduling

• Two 64-bit DDR2/DDR3 SDRAM memory controllers with ECC and interleaving support; datapath Acceleration Architecture
• Two 64-bit DDR2/DDR3 SDRAM memory controllers with ECC and interleaving support; datapath Acceleration Architecture

APPLICATION AREAS

Enterprise and service provider routers, switches, media gateways, base station controllers, radio network controllers (RNCs), access gateways for Long Term Evolution (LTE) and general-purpose embedded computing systems in the networking, telecom, industrial, aerospace and defense markets

Contact Information

Freescale Semiconductor

7700 West Parmer Lane
Austin, TX, 78729
USA

toll-free: 800.521.6274
www.freescale.com