PLS’ Universal Emulation Configurator opens up the full potential of emulation devices from Freescale and STMicroelectronics

Optimal development, test and debug environment for MPC57xx and SPC57x microcontrollers

The Universal Emulation Configurator (UEC) from PLS Programmierbare Logik & Systeme is now also available for the emulation devices MPC57xx from Freescale and SPC57x from STMicroelectronics. With the help of this special tool for definition of trace and measurement tasks for on-chip emulation logic, the full potential of the emulation devices can be used for the first time without any limitations for troubleshooting and software quality assurance.

The MPC57xx and SPC57x emulation devices are pin-compatible to their respective production chips, but include additional emulation memory, extensive trigger and filter logic as well as connections for a serial high-speed interface based on the Aurora protocol. In order that developers can easily as possible and abstractly configure the several hundred registers of the additional emulation memory, the Universal Emulation Configurator (UEC) is based on a three-stage programming model. The assembler-like Trace Qualification Language (TQL) of the first stage uses the resources of the emulation hardware. In this way, the individual register values can be set. The C-like High-Level Trace Qualification Language (HTQL) of the second stage already allows a more abstract description of measurement tasks by conditional actions and definitions of state machines. The third stage of the abstraction and the actual user interface is formed by a graphical editor, with which a measurement task can be put together from predefined blocks. In doing so, specific states in the target are described by signals. These, in turn, can initiate actions or shift an underlying state machine into a new state. The individual blocks, which serve to describe signals, actions and basic elements of state machines, are in turn grouped together in libraries. These can be extended as required or supplemented with own libraries. In order to achieve the optimal level of modularity, flexibility and user-friendliness, Extensible Markup Language (XML) was chosen as data format. Analysis tasks, which were created on the basis of the library elements, can also be saved in XML format for later reuse.

For a single block, its appearance in the editor, the parameter for adaptation to the respective measurement task and a template of the Hyper-Text Query Language (HTQL) code fragment to be
generated are described. It is thus possible to make any HTQL construct also available as a graphical element.

The Universal Emulation Configurator (UEC) helps the user to cope as effectively as possible with the limited resources of the on-chip emulation memory. In parallel to this, the implemented Aurora interface offers the possibility to externally record a very large amount of trace data and to carry out a statistical analysis of the program flow such as code coverage and profiling. PLS’ Universal Access Device 3+ (UAD3+) with Aurora pod serves for recording, while the evaluation itself is carried out by the Universal Debug Engine (UDE).

PLS Programmierbare Logik & Systeme GmbH

PLS Programierbare Logik & Systeme GmbH, based in Lauta, Germany, was founded in 1990 by Thomas Bauch and Dr. Stefan Weisse. With its innovative modular test and development tools, the company has demonstrated for over two decades its position as an international technology leader in the field of debuggers, emulators and trace solutions for 16-bit and 32-bit microcontrollers. The software architecture of the Universal Debug Engine (UDE) guarantees optimal conditions for debugging SoC-based systems. For example, by means of the intelligent use of modern on-chip debugging and on-chip trace units, valuable functions such as profiling and code coverage are available for the system optimization. Furthermore, the associated Universal Access Device (UAD2/UAD3+) product family, with transfer rates of up to 3.5 MBytes/s and a wide range of interfaces, offers entirely new dimensions for fast and flexible access to multi-core systems. Important architectures such as TriCore, Power Architecture, XC2000/XE166, ARM, Cortex, SH-2A, XScale and C166/ST10 as well as simulation platforms of different vendors are supported. For further information about the company, please visit www.pls

Contact Information

pls Development Tools

Lauta, 02991,

toll-free: + 49 – 35722 – 384 – 0
fax: + 49 – 35722 – 384 – 69

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