EECatalog Tech Videos
Debugging Heterogeneous Multicore System based on TI OMAP-L138 with Enea Optima Development Tools. Hosted by Mattias Bertilsson, Director of Product Management at Enea.
Sean Koehl from Intel Labs shows how future computers powered by multi-core processors will be able to bring amazing 3-D visuals and the ability to intelligently manage digital media, allowing you to record and view just the highlights you want to see.
Interview by John Blyler with Max Domeika from Intel
Featured White Papers
Distributed systems range from simple multi-threaded applications to multi-slot chassis-based systems to networked clusters of servers. Topologies get more complex when these systems move into cloud-based environments, and more diverse when they involve machine-to-machine (or M2M) solutions. Providers of distributed system software solutions face a number of challenges in building, debugging and maintaining a set of connected applications. Managing these systems requires powerful modeling and a variety of management interfaces to meet a diverse set of needs. The services provided by a distributed system often require a high level of availability. The middleware frameworks that make up Enea Element address many of these challenges.
Traditional high-performance computing platforms are limited by the connection bandwidth and latency between the multiple computing elements needed to achieve the performance targets. For the embedded market, the difficulty is compounded by the demanding environmental requirements. The VPX standard resolves this limitation with a large number of high-throughput point-to-point connections between the processing elements in a rugged mechanical structure.
OpenVPX System Bandwidth: A comparison of 10Gb Ethernet Performance, Serial Rapid IO, and InfiniBand
This paper compares the bandwidth available to two common types of dataflow for systems based on the VITA 65 CEN16 central switched topology, using three different fabrics – Serial RapidIO (SRIO), 10 Gigabit Ethernet (10GbE), and Double Data Rate InfiniBand (DDR IB).
A CGL compliant, high performance, high availability carrier grade Linux designed for next generation multi-core network architectures.…
This white paper takes a fresh look at the performance of low-power x86 CPUs, now that VIA has introduced dual-core and quad-core CPUs.
Market demand continues to grow for high-performance imaging, communications and security systems. Solutions need to contain scalable power-efficient processors with better integrated graphics capabilities than ever before. From imaging to communications to security to raw scalar throughput, the second generation Intel® Core™ processors (formerly codenamed Sandy Bridge) combining with C206, Q67 and QM67 chipsets offer either a simple, power-efficient upgrade or a massive architectural simplification.
At the Consumer Electronics Show (CES) on January 7, 2010, Intel® announced 27 new processors in its Core® i3, Core® i5 and Core® i7 families. Significantly for the embedded industry, twelve of these were targeted specifically at embedded applications. Early indications are that the Core i7 will offer either more processing performance per watt compared with earlier products (estimated at around 20%), or lower power consumption per unit of processing performance than its predecessors.