Compatible Operating Systems: Linux

Supported Architectures: Works with ARM, MIPS, PowerPC, and CEVA processors

Codelink delivers source-level debug and trace for instructions executing on RTL processor models. Codelink enables interactive HW/SW debug when processor instructions are used to drive stimulus into a design and monitor the results. During simulation, Codelink creates a software log-file which, in conjunction with a HW logic signal waveform log-file, can be replayed forward and backwards with complete synchronization between the source code, assembly instruction, register, and waveform views. A lengthy batch simulation can be replayed in seconds, eliminating the need to re-simulate a failing test in order to debug it.

For multi-core design, Codelink simultaneously monitors multiple processors. Any mix of supported processors can be logged during a single simulation. The Codelink debugger presents source, memory, register, variable, and call stack windows for each core in the design. All processor views are completely synchronized with the HW signal views of the logic simulator.

Codelink non-intrusively connects to existing RTL or DSM models in read-only mode. Patent-pending technology transforms general-purpose processor register info into a rich source-code debug environment. Codelink dramatically reduces the time it takes to isolate the cause of a failing RTL or DSM-driven simulation. There’s no need to rerun time-consuming batch runs in order to isolate the cause of failure.

FEATURES & BENEFITS

• Isolates processor-driven test failures in minutes; replays overnight simulation in seconds
• Dramatically reduces debug time for processordriven tests
• Interactive post-simulation debug logs processor registers during simulation and synthesizes complete dataset for interactive post-simulation debug
• Ability to trace executed code so user may step backward or forward through source or assembly, a critical feature for pinpointing the cause of a failure. Stepping through a suspect segment quickly pinpoints the errant logic
• For multi-core designs, Codelink simultaneously monitors multiple processors. Any mix of supported processors can be logged during a single simulation

APPLICATION AREAS

Audio, automotive, broadband solutions, digital cameras, DTV and STB (set-top boxes), DVD, home entertainment, imaging/video, mobile electronics/ wireless, networking, office automation, smart card & security, storage, VOIP

AVAILABILITY

Currently available

Contact Information

Mentor Graphics

8005 SW Boeckman Rd.
Wilsonville, OR, 97070
USA

toll-free: 800-547-3000
seamless_info@mentor.com
http://www.mentor.com/fv