Taking a Risk on RISC-V, an Open Source ISA



The payoff could include increased transparency, with time savings and error avoidance

RISC-V is an open Instruction Set Architecture (ISA), named thus because it is the fifth Reduced Instruction Set Computer (RISC) ISA developed at UC Berkeley. The base ISA was designed to be simple, clean, and similar to other RISC instruction sets. In 2015, RISC-V was officially kicked off by the RISC-V Foundation as a zero cost, royalty- and paperwork-free ISA. Today, there are three different RISC-V instruction sets with address sizes in 32-, 64-, and 128-bits. The RISC-V Foundation, with more than 100 members, believes that RISC-V has potential to dominate computing from embedded and small form factors all the way to warehouse servers. The Foundation creates and manages working groups to guide future development. RISC-V Foundation members include Berkeley Architecture Research, Google, Microsemi, NVIDIA, Qualcomm, Western Digital, IBM, NXP, Samsung, Express Logic, Siemens, and many others.

Why not have a standard ISA? An ISA is a vital interface where hardware meets software. After several decades, computing seems to have reached a consensus favoring Reduced Instruction Set Computers (RISC). Even Complex Instruction Set Computers (CISC) are using RISC “under the hood.” Although there seem to be many open projects in many areas, until recently, there has been no open source ISA for open and free implementation. ISAs add a necessary but considerable amount of cost to computing. To port software from one ISA to another ISA is expensive. Systems-on-Chips (SoCs) have many different ISAs, but ISAs do not affect system performance or energy efficiency as much as algorithms, compilers, circuit design, or fabrication processes, making RISC-V a good candidate for open use.

The benefits of RISC-V include a shorter time-to-market, fewer errors given more developers are looking at it, lower cost from reuse of the open ISA, and transparency that makes it difficult for governments or nation-states to add secret trapdoors. The fabless Arm has successfully proven that a company can come up with the IP for an instruction set or processor and that many others will fabricate it. It is much easier for designers to take an open ISA and change or add proprietary sections for reuse. An industry-standard ISA lends itself to a larger population of engineers with a collective experience, ecosystem, and community forums. Architecture research and education would be more realistic and able to leverage fully open hardware and software stacks. Open source makes products such as the Internet of Things less expensive. RISC-V can span the small to the large in computing. Historically, standards bodies have cooperated together for many other open technologies, but not an ISA. Until now.


Lynnette Reese is Editor-in-Chief, Embedded Intel Solutions and Embedded Systems Engineering, and has been working in various roles as an electrical engineer for over two decades. She is interested in open source software and hardware, the maker movement, and in increasing the number of women working in STEM so she has a greater chance of talking about something other than football at the water cooler.

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