As systems handle larger amounts of data, the need to transfer that data in short amounts of time demands that the interfaces such as the popular universal serial bus and PCI express operate at higher speeds. Just such efforts to define the next-generation USB and PCIe interfaces that operate at data rates of 300 Mbytes/s for USB 3.0, and up to 8 Gtransfers/s for PCIe 3.0 are underway by both the USB special interest group and the PCI special interest group. These data rates can cut the current data transfer times by at least fivefold for USB as Table 1 shows by comparing the three generations of USB transfer speeds for different size file transfers. Similarly, PCIe 3.0 delivers double the transfer rate over PCIe 2.0 as shown in Table 2.

Also referred to as SuperSpeed USB, the next generation USB interface includes a “Synch and Go” capability and was designed to work in mobile platforms thanks to extensive power management embedded in the media-access-control (MAC) and physical interface (PHY) portions of the controller. This interface will provide plenty of headroom for all the flash-memory-based peripherals such as digital cameras, camcorders, memory drives, smart phones, as well as many industrial systems that are embracing flash storage.

What’s different in USB 3.0? – aside from the higher data transfer speed, designers added a dual-simplex data path and revised the USB protocol without requiring any auxiliary signals (no reference clock, no reset signal, etc.). Figure 1 shows a side-by-side comparison of the two interface signal sets and the two additional twisted pairs for the dual-simplex data path incorporated in the USB 3.0 cable. However, the cable interface remains backward compatible with USB 2.0, with the basic 2.0 interface remaining intact. For peripherals and other operations, operations, though, only one bus connection is allowed to be active at any point in time. Inside the hubs, though, USB 2.0 and 3.0 bus trees will operate independently of each other. For compound peripherals that have integrated hubs, the multi-bus operation is only allowed for the hub portion of the peripheral.

The Superspeed interface can support up to a 3 meter cable and deliver up to 300 Mbytes/s for storage-class devices. Connectors used for the interface can fit the current USB 2.0 Type-A and Micro-B form factors and systems retain the USB hot-plug capability, thus making the use of the SuperSpeed interface almost transparent to the user. However, the Standard-B connector is visually different from the USB 2.0 Standard-B connector, but USB 2.0 cables can plug into the USB 3.0 Standard- B connector. The Micro –B connector for USB 3.0 is an extended version of the 2.0 Micro-B connector that adds a second connector section for the additional signals required by USB 3.0; however, USB 2.0 Micro-B connectors can plug into the 3.0 version of the connector.

When comparing the SuperSpeed USB interface to other highspeed interfaces such as SATA or PCI Express, there are a few differences – SuperSpeed USB does not use a common clock architecture, but does require the use of spread-spectrum signaling on both sides of the interface. Additionally, equalization is required on the receive side of the interface. The link layer was designed to be robust, with redundancy and advanced encoding techniques as well as error management incorporated in the link layer.

Additionally, both the upstream and downstream ports can initiate lower-power states on the link to provide control of the four power states incorporated in the link layer to minimize power consumption during idle periods. The four states are defined as U0 (active data transfers), U1 (link idle but internal PLL remains on), U2 (link idle but PLL may be off), and U3 (suspend). In situations in which the host initiates a transfer to a device that is connected through a hub, and the link on the device side of the hub is in one of the low-power modes, the hub will send a deferred command back to the host, and then will forward the original packet header to the device, thus waking up the device. This allows the host to initiate transfers with other devices while the initial device is wakes up and notifies the host it is ready to complete the transfer. Thus the host never has to wait for a device and that maximizes the data throughput

Moving data over the link includes three steps – link training, packet formation, and error handling. Data packets contain both a header and the data payload, and transaction packets manage the f low of data. The USB host initiates all data transfers, while devices can respond immediately or defer their response. Deferred requests are restarted asynchronously, with the device notifying the host, which responds with a new transfer request.

For high-speed transfers within a system, PCI Express has become the dominant interface in PC and industrial systems. However as fast PCIe 2.0 is, it’s not fast enough for high-performance graphics and other data intensive applications. To meet the speed demands, designers are now close to finalizing the specifications for PCIe 3.0, which will offer data transfers of up to 8 Gtransfers/s. Basically, PCIe 3.0 will be backwards compatible with PCIe 1.x and 2.0 (no changes to the connectors, card form factors, or material) and preserve existing data-clocked and common-clock architectures. The PCIe 3.0 channels will also have a similar “reach” on the system boards – for mobile applications, up to 8 inches with one connector; in desktop systems, up to 14 inches with one connector; and in servers, up to 20 inches with two connectors.

Table 1: Comparison of data transfer rates for three generations of USB interfaces

Table 2 – Data transfer rates for the three PCIe generations

The PCIe 3.0 PIPE (PHY interface for PCI Express) is an extension of the PCIe 2.0 PIPE, adding 32-bit data widths (up to 32 parallel serial channels), new clocking options, and a new control signal for the MAC to tell the PHY to ignore eight bits. Additionally, the MAC uses the control signal to handle 128/130 bit domain rate differences. The PIPE layer handles the low-level PCIe protocol and signaling, which includes functions such as data serialization and deserialization, 8b/10b encoding, 128b/130b encoding, as well as the analog buffers, elastic buffers, and receiver detection.

To add more f lexibility to the interface, the forthcoming spec will include an atomic read-modify-write transaction capability to extend interprocessor synchronization mechanisms to the I/O. Additional features added to the 3.0 interface include an ID-based transaction ordering capability that can help reduce transaction latencies in a system and a multicast transaction capability that permits performance scaling of existing applications and could open up new usage modes for PCIe. The spec also includes more dynamic power/thermal control capabilities to better handle high-power boards such as graphics processors that are plugged into the interface (up to 300 W for an add-in card).

Want more information? Go to the USB Developer website, www.usb.org., or for PCI Express 3.0, go to www.pcisig.com.

Dave Bursky is a contributing editor for Chip Design and Chip Design Trends. He also is the technical editorial manager at Maxim Integrated Products Inc. in Sunnyvale, CA.