Launched in 2002, the first generation of PCI Express (1.0) supported 2.5GT/s and transitioned from the existing parallel data architectures to a serial data technology to provide a roadmap for continued performance improvements. A number of goals drove the initial development of the PCI Express specification, including consolidating the PCI, PCI-X and AGP interfaces; increasing performance; overcoming timing and layout issues with PCI; and improving quality of service (QoS). For the most part, PCI Express achieved all of these goals and quickly replaced the AGP and PCI-X interfaces in designs. While PCI has endured a bit longer, it is only a matter of time before PCI Express replaces it as well due to the inexorable demand for more speed.

Although the first generation of PCI Express supported 2.5GT/s, there were immediate requests for additional bandwidth as products in the enterprise computing segment required performance beyond what PCI Express 1.0 provided. To meet this demand, the PCI Express 2.0 specification, which supported 5.0GT/s (Gen2), was rolled out to designers in 2005 and 2006. Yet again, there were almost immediate requests by the enterprise computing markets for additional functionality and, of course, more performance. The new functionality of the PCI Express specification included a number of engineering change notices (ECNs) to improve system-level issues targeting performance, the software model, the communication model and power management. In addition to these ECNs, Single-Root I/O Virtualization (SR-IOV) and Multi-Root I/O Virtualization (MR-IOV) technologies were built on top of PCI Express to allow the sharing of I/Os in enterprise computing systems. I/O virtualization in enterprise computing systems is migrating from a predominantly software implementation to incorporate more virtualization functionality into hardware, improving performance and reducing the costs in these systems. The PCI Express 3.0 specification (Gen3) first emerged in 2008 providing further performance improvements, including support for 8.0 GT/s, with products expected to ship in 2010.

As the PCI Express standard continues to evolve, it will be interesting to look at the markets it serves and the effects the updates will have on SoC designs. Industry reports and market surveys have separated the markets into traditional segments, such as PC, storage, networking, consumer, automotive and aerospace. Although segmenting the markets this way can be useful, a simpler way to view the market is to categorize them based on the PCI Express features used. When doing so, the market divides into the following segments: the PC industry (a well known market limited to chipsets and graphics card providers), connectivity and enterprise computing.

The connectivity segment contains products that provide expandability into systems and consists of replacements for existing PCI and PCI-X interfaces used in PC add-in cards, basic networking chips (i.e., 10M/100M/1G Ethernet), 1394, embedded systems, multifunction printers, wireless hubs, etc. This segment uses limited features of PCI Express and is under constant pricing pressure since many of the end products target the consumer market. In this segment, PCI Express designs are generally singlelane (x1) PCI Express endpoints running at 2.5GT/s.

The enterprise computing segment is made up of products used in data centers, such as blades, networking, and storage devices and servers. These types of products crave additional bandwidth and are the ones pushing the performance requirements of PCI Express. This segment uses PCI Express to build endpoints (EP), root complex (RC) and dual mode (EP/RC) devices, which are usually eight (x8) or sixteen (x16) lanes and currently support PCI Express 2.0 using 5.0GT/s. Many of the companies in this segment are already moving to the PCI-SIG SR-IOV technology in their next designs, and demand increased bandwidth beyond the PCI Express 2.0 standard.

The industry is currently working on the PCI Express 3.0 standard and looking to achieve another doubling of bandwidth. Instead of doubling the speed from 5.0GT/s to 10GT/s, PCI Express 3.0 will use 8.0GT/s, which simplifies the design of the PHY by enabling the use of linear equalization techniques instead of the more complex decision feedback equalization (DFE). The lower speed also allows designers to continue to use less expensive, standard FR4 board materials. The other 20 percent improvement comes through changes to the protocol, including changes to the composition of the packets and the removal of 8b/10b encoding. The PCI Express 3.0 interface will, of course, be backwards compatible to PCI Express 1.0 and 2.0, so the digital controller will have to support the old definitions and be able to switch in these new protocol changes when up shifting to the faster speeds.

As PCI Express continues to evolve, it is interesting to note that the PCI Express markets are still essentially defined by the original markets served by AGP, PCI and PCI-X (i.e. the PC industry/graphics, connectivity and enterprise computing). Even though the needs for each of these groups are different, they all have come together under the PCI Express specification and driven it to wide adoption. With the connectivity market being fully served by single-lane, PCI Express 1.0 and the enterprise computing market migrating from PCI Express 2.0 (5.0 GT/s) to PCI Express 3.0 (8.0 GT/s), it leads one to wonder what the lifespan is for PCI Express 2.0? Will PCI Express 2.0 be quickly replaced by PCI Express 3.0, or is it possible that PCI Express 2.0 will develop into a smaller connectivity market for high-end adapters? With the doubling of performance of PCI Express 3.0 over PCI Express 2.0, it is expected that designers will quickly incorporate this latest version to address the high bandwidth needs of their next-generation enterprise computing products targeted for 2010.

Incorporating the PCI Express interface into the latest designs will pose some challenges for product developers in terms of managing the latest errata, ECNs, I/O virtualization technologies and 3.0 features. Furthermore, ensuring that the interface is completely validated, compliant and interoperable with other PCI Express devices will be critical to product success.

Scott Knowlton joined Synopsys in1997, and is currently a Sr. Product Marketing Manager in the IP group. Knowlton is responsible for Synopsys’ market-leading PCI Express, PCI-X and PCI IP product families, and was previously responsible for the AMBA and coreTools product lines. Prior to Synopsys, Knowlton worked in simulation, synthesis and mixed signal solutions at Cadence Design Systems after having held several en¬gineering and project management positions in ASIC development at Encore Com¬puter, Intrinsix and Raytheon. Scott earned his Bachelor of Science degree in Electrical Engineering from the University of Michigan.