Since it’s introduction in 2004 by Intel, IBM, Dell and HP, adoption of the Peripheral Component Interconnect Express (PCIe) protocol standard has moved along at a healthy pace, with the PCI SIG industry group now working on revision 3.0, which achieves twice the effective data throughput rate of the current PCIe 2.0 standard through a combination of increased data bit rate (5 GT/s moving to 8 GT/s) and the elimination of 8b/10b data encoding, which previously added an overhead of 20 percent to all data transfers.

For your reference, the following table summarizes PCIe 3.0 datarates.

This faster data rate is allowing application of the protocol in new ways with the wireless market a prime example. Here, a surplus of new radio frequency (RF) technologies have emerged creating opportunities for solving old problems in new ways and requiring techniques such as flexible high-resolution waveform generation, digitization and analysis subsystems capable of manipulating RF signals in conjunction with down-conversion and tuning multiple “regions of interest,” according to Jim Henderson, president of Simi Valley, CA-based Innovative Integration (www.innovativedsp. com). Subsequent, real-time, multi-channel demodulation of these regions using a variety of schemes is necessary and many times, the equipment must be portable and operate under harsh environmental conditions. This creates challenges in packaging, power consumption and management.

To address this, existing products use arrays of dedicated digital signal processors (DSPs) working in tandem with an RF digitizer to provide the computational bandwidth needed to implement down-conversion and demodulation functions, he explained. And while it is effective, this approach is complicated and expensive since multi-processor programming requires sophisticated process management and load balancing while avoiding race conditions and data bottlenecks.

Further, there are modular devices coming to market that leverage the industry-standard, commercial-off-the-shelf (COTS) COMEXPRESS PC architecture and development tools in conjunction with PCI Express-based XMC mezzanine modules to create costeffective, customizable RF processing block solutions, Henderson said. Use of advanced PCI Express PMC modules allows highperformance FPGA-based computational engines to be used that can be dynamically loaded with customized firmware to address changing RF processing requirements and markets.

From the test perspective, LeCroy Corporation (www.lecroy.com) has a line of protocol analyzers that helps engineering teams understand, monitor and document PCI Express traffic between root complexes and endpoint devices in a number of ways. LeCroy product marketing manager John Wiedemeyer has observed the biggest area for growth currently is in graphics cards with high speed I/O such as 10Gbps Ethernet, SATA and others.

He noted that while development of PCIe 3.0 is still in the works, the current revision is often more than enough for many customers. “As the industry moves away from the PCI standard, vendors are scrambling to support PCIe, which many times, is actually overkill for the application,” he said.

Still, since new microprocessors support PCIe, so must the system. A bridge chip can be used at first to support a new revision, eventually, the entire system must be upgraded, which also gives the benefit of a performance boost.

LeCroy serves many markets for embedded applications from slot machines and airplanes to HPC servers all of which leverage PCIe, Wiedemeyer said. For these customers, one challenge to overcome can be utilizing all the performance that the protocol promises, with a big problem for some users being card performance. “The PCIe protocol is sufficiently sophisticated for customers to implement but they may not be getting all the performance they could,” he offered.

In response to this and recognizing the market need to take apart the protocol, LeCroy brought its Gen 2 protocol analyzer to market in 2003, and has very recently introduced its Summit™ T3-16 PCI Express protocol analyzer to support the PCIe® 3.0 specification that captures, decodes and analyzes PCI Express bus traffic at data rates up to 8 GT/s per lane on bus widths up to 16 lanes.

Changes in Server Market Impacting PCIe

Alex Goldhammer, strategic marketing manager for PCI Express at Xilinx Inc. (www.xilinx.com) said changes in the server market are driving much of what’s happening for PCIe.

One example of this is Cisco entering into the datacenter market, mostly through the acquisitions of Nuova in April 2008 and Tidal Software, Inc. in April 2009, along with the introduction of the Nexus 5000 series which contains 8 blades, each of which is 2-socket server.

“I have a feeling this has a lot to do with what is driving PCI Express,” Goldhammer said. “In terms of Cisco, the first step for them was collapsing the network on the storage and LAN. There is now a single Ethernet network with transport of Fiber Channel over Ethernet and traditional LAN data.”

“In terms of PCI Express in enterprise equipment, everything else has been virtualized, the only thing left to virtualize is the I/O. That’s the next big trend,” he continued.

Intel, for example, has helped extend virtualization technology by adding Intel Virtualization Technology for Directed I/O (VT-d) in the latest Nehalem Processors and Tylersburg chipsets. What this technology effectively does is hardware accelerate the address translation that used to be done in the virtual machines (VM). This enables near full-speed I/O for the virtual machines.

Another reaction in the market is the acquisition of Sun Microsystems by Oracle. “For a company like Oracle, they haven’t really had to directly build hardware for their database software. The Oracle acquisition of Sun appears to be an effort to make sure Oracle has continuity in their hardware for their customers. Sun has also opened up their operating system, OpenSolaris, which will better enable migration to different server hardware such as the x86 architecture in the mainstream,” Goldhammer noted.

“In the I/O space, Xilinx plays a big role in hardware acceleration. ASSPs are very good for single function. However having a programmable endpoint allows our customers to do different kinds of hardware acceleration directly in the PCIe end-point. In the context of the networking space, you can do packet processing, encryption, compression or run various protocols in that endpoint or even upgrade that endpoint to support new and emerging applications,” he asserted.

A general trend – albeit a surprising one – is that Intel is giving companies like Freescale and AMCC a bigger run for their money, Goldhammer noted. “In the past, there was a much broader set of processors and now Intel is moving into vertical markets where they didn’t play before. The cost per performance of Intel is very attractive in the low/mid end where it is becoming increasingly challenging for companies like Freescale and AMCC to compete. With Intel’s multiple core processors it is making it increasingly easy to offload co-processing to one of these Intel processing cores. AMCC and Freescale are going to have to move increasingly in to the high-end to provide high-bandwidth specialized functionality.

Further, in terms of vertical market spaces, the medical market is also quite dynamic, Goldhammer said. Xilinx plays a big role in Medical Imaging where two-socket servers are used in conjunction with specialized PCI Express add-in cards with Xilinx FPGAs.

“It’s a very specialized kind of processing that lends itself well to something like a Xilinx device. It is a classic case of a customer using off-the-shelf hardware that has a good cost point and their putting time and resources into their value-add FPGA to perform specialized functionality that lends itself well to the FPGA,” he added.

In a similar fashion, there is a lot of work going on in the video market, Goldhammer said. “With many different devices on which to view the same content, content providers have challenge serving that content. With video being targeted on devices ranging from iPhones to 1080p HD TVs video processing to perform specialized functions such as image correction, image sizing, and security, all lend themselves to FPGA technology.

Goldhammer views the biggest challenge in designing for PCI Express as dealing with serial technology. Xilinx’s latest Spartan-6 device contains PCI Express in an integrated block and also includes transceivers – which is a serial technology. “What that means is that for a large portion of our customer base this will be the first time working with serial technology. With Spartan-6 and PCI Express a where many customers do not have the expertise on how to build a board with high-speed serial, how to simulate signal integrity, or how to route the signals off of the chip, and so forth.”

To account for this, Xilinx developed what it has named the Targeted Design Platform to provide a framework for customers to develop around specific applications and technologies, and to quickly develop with serial technology such as PCI Express.

Ann Steffora Mutschler is Editor of Extension Media’s EECatalog Resource Catalogs, and is also a Contributing Editor to Chip Design Magazine’s System-Level Design and Low-Power Design Communities. Her previous experience includes a long stint as a Senior Editor at Reed Business Information for publications including EDN, Electronic News and Electronic Business. She has moderated a number of panels in Silicon Valley and has written for publications worldwide.