Three Generations of Choices for Developers



 

With the announcement of the PCI Express Gen 3.0 specification last year, embedded developers have more options than ever. While Gen 2 or even Gen 1 still meet the needs of many applications, newer designs – especially those that are graphics– and storage–heavy – can take advantage of Gen 3’s higher performance, doubled bandwidth and optimized power capabilities. We talked to John Wiedemeier, senior product marketing manager for LeCroy, Akber Kazmi, marketing director for PCI Express switches at PLX Technology and Niels Enevoldsen, senior field applications engineer at ADLINK Technology, Inc. to get their take on the options PCI Express offers developers.

EE Catalog: What are some of the most important roles PCI Express plays in the embedded space?

4_a

John Wiedemeier, LeCroy: There are several areas where PCI Express is helping embedded development. For example, it is providing higher and more scalable performance capabilities for embedded designs. Many embedded designs are moving from the older PCI–based I/O architectures to PCI Express. Another important way PCI Express is adding value is providing an off–the–shelf technology that enables developers to reduce costs and improve time–to market. In addition, older designs can benefit from the new PCI Express switch chips introduced in the last couple of years that can boost their existing I/O capabilities.

 

4_b

Akber Kazmi, PLX Technology: PCI Express has gone through three generations of speed upgrades (to Gen3 at 8GT/s per lane) while maintaining a cost/performance model that suits embedded systems, along with many other form factors. It’s in heavy use in server, storage, communications and graphics, resulting in an ecosystem that greatly benefits embedded systems developers.

 

 

4_c

Niels Enevoldsen, ADLINK Technology, Inc.: PCI Express in the embedded space increases bandwidth and throughput for new embedded applications using FPGAs, image processing in high–definition video, signal processing and high–data communications.

 

 

 

EE Catalog: What are the adoption trends you are seeing in embedded applications for the different generations of PCI Express?

Wiedemeier, LeCroy: For the last several years, many embedded board companies have been upgrading their existing PCI–based designs with bridge chips to PCI Express or native PCI Express implementations. These implementations have targeted both PCIe 1.1 and 2.0 technologies. Graphics–related projects have consistently moved towards the PCI Express 2.0 technologies.

Kazmi, PLX Technology: PCI Express was adopted in VITA, ATCA and microTCA fabric architectures and has made significant progress in these areas. PCI Express Gen1 and Gen2 were broadly used in advanced mezzanine card modules, and now Gen2 and Gen3 switch fabric and expansion boxes are being introduced by many of PLX’s customers.

Enevoldsen, ADLINK Technology, Inc.: PCIe Gen1 offers adequate data transfer speed for most embedded applications I have seen so far, but high–end medical and military image/video processing would be future potential market segments.

EE Catalog: What are your thoughts on the new external cabling version of PCIe 3.0 that is in development through the PCI–SIG?

Wiedemeier, LeCroy: Although the new external cable spec is still under discussion, there are some interesting ideas being put forth. Unlike the Thunderbolt design, the new PCI Express cable will use the existing PCI Express interconnect available on the system board to make the host connection instead of being connected to a controller on the system board. System boards in future implementations could simply have a PCI Express connector or connectors that allow PCI Express devices such as PCIe–based SSDs or drives, printer, etc. to connect through this new cable. How far this model could go will depend on costs and ease of adoption by industry players.

Kazmi, PLX Technology: PCI Express Gen1 and Gen2 cabling specs have been out in the market for a while but actual products have not achieved economies of scale to reduce the cost. New applications are being introduced that demand low–cost cabling. Unlike with PCI Express Gen1 and Gen 2, we expect this new cable group, in which PLX also participates, will quickly develop a specification for Gen3 cables that addresses different markets with different form factors to meet the cost targets. There is enough momentum in the market driving the specification and ecosystem to convince us that the new specification will help the market drive down the cost. Separately but relevant to this discussion is the industry’s move to take PCI Express over optical cable, which we envision rapidly changing data center clustering schemes.

EE Catalog: How are developers addressing the challenges in adopting new PCI Express capabilities such as power–saving?

Wiedemeier, LeCroy: Low–power support has been a difficult issue for the PCIe community since its beginning. It’s a constant balancing act between exit latency, power savings and operational robustness. L0s has good exit latency, but often leads to link failure and doesn’t save enough power. L1 saves more power but has poor exit latency. Initially it seemed that many developers simply disabled the power–savings modes. However, increasing pressure to provide system–level power savings has pushed into every interface including PCIe. Many developers are doing more testing with these modes to ensure they work robustly. The protocol analysis tools can help track these low-power states and identify when link–recovery operations are occurring and why.

Kazmi, PLX Technology: In addition to power management and plug–and–play (hot–plug), PCI Express switches offer host–isolation and direct–memory access, or DMA, capabilities that allow vendors to develop products that both keep host CPUs isolated and unburdened by using non–transparent capabilities. This enables moving data around by using the switch’s DMA, eliminating the need for host CPU involvement, for better performance and user experience. The new power management capabilities are designed into newer PCI Express products but real applications taking advantage of these features are not as broad as one would expect. Further power savings have occurred as vendors such as PLX already are shipping PCI Express on 40nm and rapidly designing new products on 28nm technology.

EE Catalog: In what new applications and market segments is PCI Express emerging?

Wiedemeier, LeCroy: The big ones announced this year have been the new PCIe cable specs – Thunderbolt and PCISIG external cables. These will most likely affect the PC peripherals and workstation markets, providing an alternative to existing PC–based cables. Storage is another area where PCI Express is getting a lot attention. There have been three specifications announced this year. These are the NVM Express, Express SATA and SCSI over PCI Express. Each of these will be utilized to increase performance of SSD devices and hybrid drives. The server and high–end workstation market will benefit the most with these new technologies.

Kazmi, PLX Technology: Major changes are underway in enterprise storage by way of widespread usage in SSDs. Recently, the Non–Volatile Memory Host Controller Interface Work Group released NVMExpress specification with the PCI Express interface. Additionally, now SCSI over PCI Express (SOP) and SATAExpress are in development to provide PCI Express an even broader footprint in the embedded industry. Taking PCI Express outside this box to replace InfiniBand and some Ethernet applications is rapidly garnering interest, too. Also, Intel recently launched Thunderbolt products for consumer and prosumer applications, leveraging PCI Express technology to connect to I/O endpoints. We expect this will boost the adoption of PCI Express in many new embedded, consumer and mobile applications.

Enevoldsen, ADLINK Technology, Inc.: PCIe “Disk–On– Modules” or “PCIe DOM” are beginning to emerge, but I think it is off to a slow start as CF cards, USB memory sticks and IDE/SATA SSDs are widely adapted in the embedded market.

 


coupe

Cheryl Berglund Coupé is editor of EECatalog.com. Her articles have appeared in EE Times, Electronic Business, Microsoft Embedded Review and Windows Developer’s Journal and she has developed presentations for the Embedded Systems Conference and ICSPAT. She has held a variety of production, technical marketing and writing positions within technology companies and agencies in the Northwest.

Share and Enjoy:
  • Digg
  • Sphinn
  • del.icio.us
  • Facebook
  • Mixx
  • Google
  • TwitThis