What’s New with PCI-SIG
AI, machine learning, gaming, robotics, autonomous driving, and virtual reality are among the applications benefitting now from PCIe 4.0 while anticipating the 32GT/s performance of the PCIe 5.0 architecture
Editor’s Note: Al Yanes, President, PCI-SIG, responded to questions recently from EECatalog.
EECatalog: How are you seeing companies differentiate themselves from the competition by using a PCIe Gen 4 platform to develop 16G solutions?
Al Yanes, PCI-SIG: PCIe 4.0 is the latest released specification from PCI-SIG and delivers 16GT/s of bandwidth and lane margining capabilities. Companies can use it to gain the performance they need with the 16GT/s and with Lane Margining, in-system health information. This makes it suitable for multiple applications and markets.
EECatalog: Can you share with our readers some of the insights and practical next steps to take based on the most recent FYI testing workshops or from similar endeavors?
Al Yanes, PCI-SIG: We are seeing high interest in the PCI-SIG FYI Compliance Testing with more than a dozen PCIe 4.0 architecture solutions brought to the recent PCI-SIG Compliance Workshop. Several PCI-SIG member companies have also publicly exhibited 16GT/s technology demonstrations. Numerous vendors have 16GT/s PHYs in silicon, and IP vendors are offering PCIe 4.0 16GT/s solutions with PHYs and controllers. The ecosystem is in place to broadly support PCIe 4.0 adoption. In addition, several vendors have done interoperability between their solutions.
EECatalog: What steps should designers and developers be taking now to prepare to get the most from PCIe 5.0 and 32GT/s?
Al Yanes, PCI-SIG:
(1) Member companies should participate in the specification process through the workgroups. Non-member companies should join the PCI-SIG to participate in the PCIe 5.0 specification development process. Increased participation improves the specification and reduces the time for the industry to adopt the updates.
(2) The PCIe 5.0 specification is moving through the standards organization very quickly and is targeted for release in 2019, and the PCIe 5.0 specification draft 0.7 spec will be completed and released to members in April 2018.
(3) With the specification moving quickly through the approval process, companies should start their product planning process and look to see when they want to intercept the PCIe 5.0 specification. As mentioned previously, the specification is targeted for release in 2019, so we would expect initial products in 2019.
(4) Incorporation of the PCIe 5.0 technology will have challenges with the electrical requirements related to the connector and running 32GT/s with the channel defined for PCIe 5.0.
EECatalog: What are some of the practical implications of 32GT/s for AI, machine learning, gaming, robotics, autonomous driving, virtual reality and more?
Al Yanes, PCI-SIG:
(1): Each of these applications requires the high performance and low latency that PCIe technology can provide, and these applications are utilizing PCIe 4.0 now.
(2) The PCIe 5.0 specification is being designed to deliver even better performance at 32GT/s to support these high-performance applications, while meeting requirements for low latency and power efficiency.
(3) The 32GT/s performance of PCIe 5.0 architecture will lead the market for data throughput and be backward compatible with prior generations of PCIe technology.
EECatalog: How should readers planning to attend PCI-SIG Developers Conference 2018 prepare to get the most out of the event?
Al Yanes, PCI-SIG: Our Developers Conferences are open to all members, and attendees are able to choose from a broad range of presentations for all levels. Members will learn about the latest features for the PCIe 4.0 specification and through peer member presentations get practical input on design considerations when implementing the specification in their products. I encourage members to get involved with our work groups and contribute to the specification development process and invite new member companies to join us.