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  • Jack Erickson's Blog

    Jack Erickson's Blog

    SI Methodology for Multi-Gigabit Serial Link Interfaces (7 of 8)
    Published. February 22, 2018

    Backchannel Training Another capability related to equalization adaptation is backchannel training. Many high speed serial link protocols enable the SerDes receiver to evaluate the signal quality of training patterns sent by the transmitter, decide if it wants more or less equalization from the transmitter, communicate that request back to the transmitter, then receive another training pattern for evaluation. This process is repeated multiple times until the receiver is satisfied with the transmitter...


  • Michael Jacobs Blog

    Michael Jacobs Blog

    SI Methodology for Multi-Gigabit Serial Link Interfaces (7 of 8)
    Published. February 22, 2018

    Backchannel Training Another capability related to equalization adaptation is backchannel training. Many high speed serial link protocols enable the SerDes receiver to evaluate the signal quality of training patterns sent by the transmitter, decide if it wants more or less equalization from the transmitter, communicate that request back to the transmitter, then receive another training pattern for evaluation. This process is repeated multiple times until the receiver is satisfied with the transmitter...


  • Tom Anderson's Blog

    Tom Anderson's Blog

    SI Methodology for Multi-Gigabit Serial Link Interfaces (7 of 8)
    Published. February 22, 2018

    Backchannel Training Another capability related to equalization adaptation is backchannel training. Many high speed serial link protocols enable the SerDes receiver to evaluate the signal quality of training patterns sent by the transmitter, decide if it wants more or less equalization from the transmitter, communicate that request back to the transmitter, then receive another training pattern for evaluation. This process is repeated multiple times until the receiver is satisfied with the transmitter...


  • Jason Andrews Blog

    Jason Andrews Blog

    SI Methodology for Multi-Gigabit Serial Link Interfaces (7 of 8)
    Published. February 22, 2018

    Backchannel Training Another capability related to equalization adaptation is backchannel training. Many high speed serial link protocols enable the SerDes receiver to evaluate the signal quality of training patterns sent by the transmitter, decide if it wants more or less equalization from the transmitter, communicate that request back to the transmitter, then receive another training pattern for evaluation. This process is repeated multiple times until the receiver is satisfied with the transmitter...


  • Joseph Hupcey Blog

    Joseph Hupcey Blog

    SI Methodology for Multi-Gigabit Serial Link Interfaces (7 of 8)
    Published. February 22, 2018

    Backchannel Training Another capability related to equalization adaptation is backchannel training. Many high speed serial link protocols enable the SerDes receiver to evaluate the signal quality of training patterns sent by the transmitter, decide if it wants more or less equalization from the transmitter, communicate that request back to the transmitter, then receive another training pattern for evaluation. This process is repeated multiple times until the receiver is satisfied with the transmitter...


  • Consumerization: BYOD

    Consumerization: BYOD

    INSTALLING ATAPI ZIP DRIVE TP PCIE IDE
    Published. February 7, 2018

    I'm trying to install an Iomega Zip 100 MB Drive on an Asus Z97 64bit motherboard running Windows 10 with a PCI express ide connector to substitute for the lack of connector that the 64bit motherboards now are usually leaving the legacy ide connector disk drives out that could be ......


  • TI E2E Community

    TI E2E Community

    Blog Post: Signal Conditioning functions go mainstream in PCI Express Gen 4
    Published. January 29, 2018

    It’s been quite a while – just about seven years now – since the current PCI Express (PCIe) Gen 3 specification became official. With a swell of activity in the standard committees, a new PCIe Gen 4 specification reached version 1.0 in late 2017. As everyone already knows, PCIe Gen 4 doubles the available data rate to 16Gbps and keeps backward compatibility firmly in place. By using the same 128/130 encoding scheme and equalization training, architects hope to minimize any conversion issues...


  • Denali Memory Blog

    Denali Memory Blog

    CCIX Coherency: Verification Challenges and Approaches
    Published. January 24, 2018

    Cache coherency is not a new concept. Coherent architectures have existed for many generations of CPU and Interconnect designs. Verifying adherence to coherency rules in SoCs has always been one of the most complex challenges faced by verification engineers. Over the years, it became even more challenging with increasing number of cores in CPU clusters and introduction of the embedded L3 (level 3) cache to the coherent interconnect devices. Advent of inter-chip coherency with the new CCIX (pronounced...


  • Steven Brown's Blog

    Steven Brown's Blog

    When Arm meets Intel – Overcoming the Challenges of Merging Architectures on an SoC to Enable Machine Learning
    Published. September 25, 2017

    As the stakes for winning server segment market share grow ever higher an increasing number of companies are seeking to grasp the latest Holy Grail of multi-chip coherence. The approach promises to better enable applications such as machine learning, network processing, in-memory data base, and other large dataset tasks. Arm and its partners continue to pursue the server market long dominated by Intel. The results will be SoCs that combine Arm CPU sub-systems with high speed interfaces such as PCI...


  • Tech Deseign Forums Blog

    Tech Deseign Forums Blog

    Master the verification challenge of PCIe-based NVMe storage
    Published. May 3, 2017

    NVMe is driving the SSD market thanks to its many useful features, but at least five major challenges must inform your verification plan....


  • scalability.org

    scalability.org

    pcilist: because sometimes you really, really need to know how your PCIe devices are configured
    Published. March 29, 2017

    If you don’t know what I am talking about here, that’s fine. I’ll assume you don’t do hardware, or you call someone else when there is a hardware problem. If you think “well gee, don’t we have lspci? so why do we need this?” then you probably have not really tried to use lspci to […]...


  • Frank Schirrmeister Blog

    Frank Schirrmeister Blog

    How to Maximize Your Verification Experience at DAC 2016
    Published. June 2, 2016

    Next week will mark the annual EDA gathering in Austin. For me it is my 20 th DAC … I know, compared to some I am still wet behind my ears, but that’s only because I started my career in embedded software and actual chip development. I already outlined in my Blog “ The Top Five Trends In Verification To Watch For At DAC 2016 ”. The System Development Suite is all about the connection between different engines and the verification fabric holding them together, maximizing throughput, allowing...


  • Team Specman Blog

    Team Specman Blog

    What Does it Take to Migrate from e to UVMe?
    Published. September 5, 2012

    So you are developing your verification environment in e , and like everyone else, you've been hearing a lot of buzz surrounding UVM (Universal Verification Methodology). Maybe you would also like to give it a try. The first question that pops in your mind is, "What would it take to migrate from e to UVM e ?" Well, this is a bit of a trick question. The short answer is that if you've adopted e RM in the past, migration to UVM e will only take a few minutes. If your environment is...


  • Verification Horizons Blog

    Verification Horizons Blog

    No to Know VIP – Validated!
    Published. April 7, 2016

    We have talked about how one can go from ‘No to Know VIP’ in my 3 part series and how Questa VIP PCIe Starter Kits make a Verification engineer’s life easy. Xilinx® recently posted the “UltraScale PCIe PIPE Simulation with Mentor QVIP” YouTube video that demonstrates how easy it is to hook Questa Verification IP […]...


  • Stephane Boucher's DSP Blog

    Stephane Boucher's DSP Blog

    Introducing the VPCIe framework
    Published. August 31, 2013

    Introduction My daily work involves platforms featuring an embedded CPU communcating with a FPGA device over a PCI Express link (PCIe for short). The main purpose of this link is for the CPU to convey configuration, control, and status commands to hardware slaves implemented in the FPGA. For data intensive applications (2D XRay detector readout backend), this link can also be used as a DMA......


  • The Eyes Have It

    The Eyes Have It

    Linking PCI Express Outside The Box
    Published. January 28, 2014

    PCI Express (PCIe) has long been a dominant standard for communications inside of computers, servers and blades but sometimes you need to think (and send data) outside the box. Since the first release of PCIe cabling standard in early 2007, creative engineers have been looking to utilize this new capability as a box-to-box interconnect, in […]...


  • Signal Integrity

    Signal Integrity

    Order Your Free DVD of the DesignCon Keysight Education Forum
    Published. April 21, 2015

    At DesignCon we presented the Keysight Education Forum. The talks are now available on a free DVD. Order yours today while supplies last! DesignCon 2015 Keysight Education Forum DVD The ten presentations are: USB 3.1 Gen 2 (10 Gbps) Physical Layer Test Challenges Practical Guide to Quickly Making 100G Electrical Measurements PCIe protocol analysis for […]...


  • Laptops and Desktops Blog

    Laptops and Desktops Blog

    Samsung adding NVMe PCIe technology to M.2 SSDs
    Published. April 16, 2015

    The diminutive SM951-NVMe will be the industry's first M.2 solid-state drive to make use of the speedy technology, which will blow away SATA-based SSDs....


  • Laptops and Desktops Blog

    Laptops and Desktops Blog

    Samsung adding NVMe PCIe technology to M.2 SSDs
    Published. April 16, 2015

    The diminutive SM951-NVMe will be the industry's first M.2 solid-state drive to make use of the speedy technology, which will blow away SATA-based SSDs....


  • Adam Sherer Blog

    Adam Sherer Blog

    IBM and Cadence Collaboration Improves Verification Productivity
    Published. February 13, 2013

    Technology leaders like IBM continuously seek opportunities to improve productivity because they recognize that verification is a significant part of the overall SoC development cycle. Through collaboration, IBM and Cadence identify, refine, and deploy verification technologies and methodologies to improve the productivity of IBM’s project teams. Tom Cole, verification manager for IBM’s Cores group, and I took a few minutes to reflect on verification productivity and discuss what the future holds....


  • Team ESL Blog

    Team ESL Blog

    More Details on Post Silicon Embedded Software Verification With ISX
    Published. August 18, 2009

    Please welcome back Joerg Simon and Markus Winterholer, both from the ISX team in Germany, to the TeamESL blog for the next installment on post-silicon embedded software verification with ISX. This post is a discussion featuring Markus and Joerg talking to Malte Henzelmann and Ernst Zwingenberger of El Camino GmbH . It builds on the introduction that was provided in June titled OVM Metric Driven Verification with an FPGA-based Design . You guys built a cool demo connecting ISX to a FPGA board for...


  • NextGenLog

    NextGenLog

    #CHIPS: "Archer Supercomputer Advancing State-of-the-Art"
    Published. April 11, 2014

    Cray scored a major design win with its massively parallel XC30 supercomputer is the fastest in the U.K. for complex simulations--from cosmology to climate modeling to aircraft design--using Intel E5 processor chips and Aries interconnection fabric chips?--R. Colin Johnson @NextGenLogThe University of Edinburgh recently installed its Archer supercomputer, which ranks as the fastest supercomputer in England.Cray XC30 series chassis are based on blades with processor daughter cards (PDCs) and a peripheral...


  • Chris A. Ciufo on All Things Embedded

    Chris A. Ciufo on All Things Embedded

    Baby, You Can Drive (the PCIe clock in) My Car
    Published. May 2, 2014

    Among all the ARM-based media processors, Ethernet AVB networks, and Xilinx Zynq-based ADAS (advanced driver assistance system) safety features, it’s the humble PCI Express clock generator that really drives the car’s IVI systems. Continue reading →...


  • FPGA Blog

    FPGA Blog

    Xilinx and Alpha Data Announce Collaboratively Developed FPGA Acceleration Networking Processing Board
    Published. December 2, 2013

    Alpha Data’s ADM-PCIE-7V3 FPGA processing card uses a Xilinx-7 FPGA for a power-efficient, high-performance acceleration. The card is targeted to increasing data throughput optimizing computing cluster performance for data center applications. Read more Xilinx and Alpha Data Announce Collaboratively Developed FPGA Acceleration Networking Processing BoardTwitter @fpgablog : : Free Publications : : Jobs : : […]...


  • FPGA Blog

    FPGA Blog

    Xilinx and Alpha Data Announce Collaboratively Developed FPGA Acceleration Networking Processing Board
    Published. December 2, 2013

    Alpha Data’s ADM-PCIE-7V3 FPGA processing card uses a Xilinx-7 FPGA for a power-efficient, high-performance acceleration. The card is targeted to increasing data throughput optimizing computing cluster performance for data center applications. Read more Xilinx and Alpha Data Announce Collaboratively Developed FPGA Acceleration Networking Processing BoardTwitter @fpgablog : : Free Publications : : Jobs : : […]...


  • Practical Chip Design

    Practical Chip Design

    Teradyne/LitePoint acquires PXI vendor ZTEC: The inside story
    Published. October 31, 2013

    An exclusive interview with the principals behind this surprising acquisition...


  • Critical Links

    Critical Links

    Teradyne/LitePoint acquires PXI vendor ZTEC: The inside story
    Published. October 31, 2013

    An exclusive interview with the principals behind this surprising acquisition...


  • Now Hear This!

    Now Hear This!

    Teradyne/LitePoint acquires PXI vendor ZTEC: The inside story
    Published. October 31, 2013

    An exclusive interview with the principals behind this surprising acquisition...


  • Anablog

    Anablog

    Teradyne/LitePoint acquires PXI vendor ZTEC: The inside story
    Published. October 31, 2013

    An exclusive interview with the principals behind this surprising acquisition...


  • Brian's Brain

    Brian's Brain

    Teradyne/LitePoint acquires PXI vendor ZTEC: The inside story
    Published. October 31, 2013

    An exclusive interview with the principals behind this surprising acquisition...


  • Brian's Brain

    Brian's Brain

    Teradyne/LitePoint acquires PXI vendor ZTEC: The inside story
    Published. October 31, 2013

    An exclusive interview with the principals behind this surprising acquisition...


  • EDA Blog

    EDA Blog

    Cadence Design Systems Introduces SpeedBridge Adapter for PCIe 3.0
    Published. July 30, 2013

    Cadence Design Systems introduced a new SpeedBridge Adapter for PCIe 3.0. The adapter provides easy bring-up and fast debug of PCIe-based designs when used with a Cadence Palladium Verification Computing Platform, and is backwards compatible with PCIe 2.0-, 1.1- and 1.0a-based designs. The Cadence SpeedBridge Adapter for PCIe 3.0 is available now. Read more: Cadence [...]...


  • To USB or not to USB

    To USB or not to USB

    The World’s First 2 Wireless Routers with USB 3.0, PCI Express Blog Launches Today
    Published. November 6, 2012

      Corrected November 29, 2012 – Thanks to reader Glenn for the info – The world’s first 2 Wireless WiFi Routers supporting USB 3.0 started shipping recently fro Netgear and D-Link. The Netgear Centria (WNDR4700/4720) and the D-Link HD Media Rounter (DIR-857) support the WiFi-AC standard which promises data rates of 450 Megabits per second [...]...





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