Posts Tagged ‘RISC-V’

RISC-V is Not a Company

Monday, February 5th, 2018

RISC-V is a new open Instruction Set Architecture (ISA), named thus because it was the fifth RISC instruction set that had been developed at Berkeley. The highly flexible and extensible base ISA base was designed to be simple, clean, and suitable for direct hardware implementation. The base instructions are similar to other RISC instruction sets like OpenRISC or MIPS. RISC-V (pronounced “risk-five”) is an open standard ISA that is royalty-free and free to implement. It’s likely that there is not a significant marketing budget to establish awareness, so it’s not surprising that some can mistake RISC-V for something else. However, RISC-V is not a company, and it is not a CPU. RISC-V began in 2010 as a project at UC Berkeley by Krste Asanović, Professor in the EECS Dept. at the University of California, Berkeley, current Director of the ASPIRE lab, and Chief Architect at SiFive. Asanović wanted a simple ISA without legal issues related to intellectual property. UC Berkeley began using RISC-V in engineering courses.RISC-V Logo

According to the RISC-V Overview in the RISC-V specifications, RISC-V is “a completely open ISA that is freely available to academia and industry; a real ISA suitable for direct native hardware implementation, not just simulation or binary translation; and an ISA that avoids “over-architecting” for a particular microarchitecture style (e.g., micro-coded, in-order, decoupled, out-of-order) or implementation  technology (e.g., full-custom, ASIC, FPGA), but which allows efficient implementation in any of these.” There are many open source projects based on the RISC-V ISA.

In 2015, RISC-V was officially kicked off by the newly formed RISC-V Foundation as a zero cost, royalty- and paperwork-free ISA. The  mission statement of the RISC-V foundation is “to standardize, protect, and promote the free and open RISC-V instruction set architecture and its hardware and software ecosystem for use in all computing devices.” Rick O’Connor is the executive director of the RISC-V foundation.

The RISC-V Foundation, with more than 100 members, believes that the RISC-V ISA has potential to dominate the computing world from embedded and small form factor, all the way to warehouse data servers. The foundation creates and manages working groups to guide future development of the architecture. RISC-V Foundation members include Berkeley Architecture Research (BAR), Google, Microsemi, Nvidia, Qualcomm, Western Digital, IBM, IDT, Lattice, NXP, Samsung, Express Logic, Huawei, Siemens, Lawrence Berkeley National Laboratory, Mentor, Segger, and Princeton, IIT Madras, National Singapore Universities.

An ISA is a critical interface where hardware meets software. There seems to be a consensus on instruction sets these days. No one has built a new commercial CISC ISA in more than 30 years, and there is widespread agreement that the RISC architecture is best for general-purpose ISA. However, although there seems to be a lot of open source or open standards in many other areas, until recently, there has been no open source ISA for open and free implementation. RISC-V is set to fill the void.

Today, there are three different RISC-V instruction sets with address sizes in 32-, 64-, and 128-bits. Perhaps 128-bit addressing is deemed unneeded by some. However, the 128-bit ISA was created to ensure that RISC-V could successfully go there, and in reality, seems to have some application in addressing for huge flash drives and in security. The RISC-V base ISA has a minimal instruction set of less than 50 hardware instructions. There are also some optional standard extensions that include integer multiply and divide, atomic memory operations, compressed instruction encoding to make code size smaller, and single-, double-, and quad-precision floating point. RISC-V reserves opcode space for the unique instructions of SoCs, if needed. RISC-V is the smallest IA for 32- and 64-bit addresses. On average, RV32C, the compressed version of the 32-bit RISC-V instruction set, is 34% smaller than other 32-bit ISAs and RV64C (RISC-V 64-bit compressed) is 42% smaller than other 64-bit ISAs.

What is available for working with RISC-V?

There are several RISC-V ISA specifications available online, including user level, privileged and compressed RISC-V instruction set specifications. The RISC-V toolchain is a standard GNU cross compiler toolchain (GCC/glibc/GDB ) ported for RISC-V. RISC-V supports Linux (or…Linux supports RISC-V). RISC-V is also found in Yocto, and there is a verification suite. One of the best hardware tools for RISC-V, widely used in the universities, is Chisel. Chisel is a hardware construction language using a scala-embedded metaprogramming language. Chisel simultaneously produces a software simulator, an FPGA emulation, and a GDS Layout. Chisel is ideal for reuse (shared lines of code), and a BSD-licensed open source tool that’s available at

The time is right for an open ISA with a standard base. Sun created one years ago, but it faded. The continued rise of SoCs seems to have reinitiated the attractiveness of an open ISA that wasn’t as strong with the Sun attempt. Moore’s law is ending which means we will be moving to domain specific architectures. The definition of an ISA is that it is a vital interface where hardware meets software. Additionally, after several decades, computing seems to have reached a consensus favoring Reduced Instruction Set Computers (RISC). Even Complex Instruction Set Computers (CISC) are using RISC “under the hood.” Nevertheless, ISAs add a necessary but considerable amount of cost to computing. To port software from one ISA to another is expensive. There are many different ISAs for the many Systems-on-Chip, but ISAs do not affect system performance or energy efficiency as much as algorithms, compilers, circuit design, or fabrication processes, making RISC-V a good candidate for open and free implementation.

The Case for RISC-V

RISC-V can provide a shorter time-to-market, fewer errors given more developers are looking at it, lower cost from reuse, and transparency that makes it difficult for governments to add secret trapdoors. Arm has no fabrication plant, and yet is nearly ubiquitous in smartphones and beyond. Arm has successfully proven that a company can sell the IP for an instruction set or processor and others will fabricate it. It is much easier for designers to take an open ISA and change it or add proprietary sections for reuse.

An industry-standard ISA lends itself to a larger population of engineers with collective experience, a vibrant ecosystem, and community forums forming around a shared basis. Architecture research and education would be more realistic and able to leverage fully open hardware and software stacks. Open source makes products such as the Internet of Things less expensive. RISC-V can span the small to the large in computing. Historically, standards bodies have cooperated together for many other open technologies, but not an ISA. Until now.