GoldenGate RFIC Simulation and Analysis Software
Agilent GoldenGate provides the framework for RFmixed signal (RF-MS) designers to rapidly simulate circuits, verify specs and validate potential yield of complex highly integrated RFICs. Designers can confidently simulate blocks, combinations of blocks and full receive/ transmit chains to understand the influences introduced by noise, distortion, parasitics and numerous other effects confronted in modern RF-MS IC design. Additionally, designers can analyze the manufacturability of circuits using industry standard techniques such as Process and Mismatch Monte Carlo as well as unique Agilent statistical mismatch and process analyses.
These tools provide a comprehensive circuit simulation verification and analysis methodology that has been seamlessly integrated into the Cadence Analog Design Environment. Designers can move smoothly through schematic capture, test bench setup, simulation and analysis to achieve insight into design performance and manufacturability prior to tape out, avoiding costly mistakes and design re-spins.
Agilent’s extensive suite of RF-MS simulation, verification and analysis capabilities from system to silicon ease the design challenges. Adding GoldenGate to the design flow reduces costly design iterations, improves productivity, shortens the design cycle, and increases the probability that you can achieve success in the shortest time possible.
FEATURES & BENEFITS
- Best performance, capacity and accuracy to complete your RFIC designs on time with the highest level of designer productivity
- Delivers increased manufacturability using powerful Monte Carlo, Corners and Yield analysis capability
- Uniquely verifies 3G and 4G RF performance using standards-based system level test benches
- Fast Yield Contributor — Improve yield by optimizing only what really matters. Determine device, circuit and block yield contributions at any stage of the RFIC design flow.
- Fast Circuit Envelope Analysis — Accelerate RF functional path simulations an order of magnitude with broader support for RFIC centric source configurations for models including memory effects.