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CST invites you to a free webinar: Chip/Package/Board: constraint driven co-design

Memory interfaces have single-ended data rates in the 1GHz-plus range and serial links are running upwards of 10 gigabits per second. A precise analysis of each of these signals is required at silicon, package and board level. The design and optimization performed on each one of these interconnection levels must be done in a global context.

This webinar proposes a global methodology which combines three dimensional (3D) electromagnetic (EM) analysis for PCB and package with chip power switching macro-modeling.

Differences between a segmentation approach (where silicon, package and PCB are analyzed separately and then combined with standard cascading technique) and an integrated/global approach (where chip, package and PCB are analyzed as single entity in a co-simulation mode) are discussed, and based on the results, guidelines are outlined.

Please join us on December 6th at 8:00 AM Pacific Time, 11:00 AM Eastern Time, 17:00 CET for a 60 minute web presentation and Q&A.

Full details and registration here:
http://www.cst.com/webinar/12-12-06~/?utm_source=cst&utm_medium=email&utm_content=chip&utm_campaign=2012series

This webinar is part of a series. The series is organized in tracks dedicated to the use of 3D EM simulation in various application areas such as EDA or EMC/EMI.

More information on the webinar series can be found at:
www.cst.com/webinars

Contact Information

CST AG

Bad Nauheimerstr.19
Darmstadt, 64289
Germany

info@cst.com
www.cst.com/

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