Analog High Speed Communication Devices for 40G/100GB Ethernet Require a Totally New Approach to Test
Analog high speed communication devices are far from fitting into a standard, high volume manufacturing test process with a well-established set of best-known practices.
The Internet of Things (IoT) is going to be the next booming RF wireless market as it pushes the growth of the cloud infrastructure driven by consumer demand for ubiquitous and instantaneous access to information. We often focus, for very good reason, on how those billons of sensors and chips will be connected to the premise and access of the infrastructure, but we forget quite consistently that those data streams must also be backhauled to the core network and routed to the appropriate data-center. Bandwidth in the optical network and datacenter is already starting to catch-up with the ever growing demand in mobile and video data. The Cisco IP traffic survey (Figure 1) shows bandwidth demand rising at the infernal pace of 48% CAGR.
Figure 1. IP Traffic trend and usage ratio.
To avoid being overwhelmed by this data tsunami, the industry has answered with aggregating more bandwidth. Both the infrastructure and service providers have started to deploy Ethernet high speed links at 40Gbps and 100Gbps mainly at the top of their network for aggregation routers and switches and long haul transponders. The 100G Ethernet, based on optical components, is rapidly displacing the 10G workhorse of the last decade in the telecom and datacom industry. Figure 2 from a recent IHS-Infonetics Research report does put a spotlight on the inevitable arising of the 100G era in the network.
Figure 2. Transmitted capacity per link data-rate.
Analog no longer means slow
Technologically, analog means more wireless spectrum in the radiofrequency, and more optical wavelengths and higher modulation bandwidth in the optical transport network (OTN).
On one hand, RF telecom backhaul transceiver devices do move progressively to the 60 GHz (V-band), and the 70-80-90 GHz (E-bands) and their respectively 7 GHz and 10 GHz of available spectrum to be compared with 80 MHz in 802.11ac and maximum 20 MHz LTE channels occupied bandwidth in the cellular space. Millimeter wave backhaul transceivers do aggregate link of capacity above 1 Gbps, reducing then the necessary need of a fiber to each radio head on the tower sites.
On the other hand, 100G Ethernet optical ports do need optoelectronic devices in optical module and telecom line cards, such as Trans-impedance amplifiers (TIA) and Mach-Zehnder Modulator drivers (MzMD). Those devices have to enable a 40 GHz signal bandwidth amplification and modulation with key linearity constraints either for short or long reach OTN applications.
From an electrical test perspective, those analog high-speed communication devices are very different from their digital high-speed serial devices and 40Gbps SerDes macros also included into the CFPx optical module as illustrated by the Figure 3.
Figure 3. Block diagram of a 100GB Ethernet client CFP to linecard interface.
Analog high speed is a different test paradigm
Digital high speed serial devices benefit from the CMOS integration of test features, such as BIST and DFT enabling functional testing in loopback, eye-monitoring embedded features inside the same piece of silicon. As a test engineering work it is mostly a digital macro go/no go testing with loopbacks on the test load board or even on-chip TX/RX. During chip characterization, Automatic Test Equipment (ATE) does answer that need with specific digital BER testing options. Intrinsically the wafer level test does not actually differ from the SoC mainstream test flow, and is exclusively a time domain testing (TD) at package level (on large fan-out BGA). This final test implies short test time helped by the parallelism offered by the mainstream ATE.
It is a totally different paradigm with the high speed analog chips in the optical network serving as the analog front-end of the CFP client module. TIA devices exhibit 4 analog differential channels/lanes at 25Gbps and MzM Drivers 4 quadrature channels both over a 40 GHz bandwidth. The former is directly associated to the photodiode detector (one diode per Lambda) and, the latter is directly associated to the optical modulator still in III-V hybrid substrate. Figure 4 illustrates the RX/TX optical module interface on a long haul coherent optical CFP.
Figure 4a. Optical Transmitter (TX) with MzM Driver IC in blue.
Figure 4b. Optical Receiver (RX) with MzM Driver IC in blue.
The TIAs and MzM Drivers integration requires thus to be carefully assembled into the multichip module still maintaining cutting-edge 40 GHz bandwidth stable gain, and insertion and return loss. If CMOS silicon analog performance is always getting better, those high-speed analog devices are manufactured mainly in III-V and BiCMOS process, still 8 inch wafers. Indeed if RF-CMOS manufacturing process can still promise acceptable 1/f noise, Noise Figure (NF), and even better quality passive or transmission line on HR substrate, it cannot sustain both a crucial NF at 50 Ohms over 40 GHz bandwidth and provide a FMIN and associated sufficient Gain as a function of a low bias current compared with BICMOS SiGe and InP HBT.
Figure 5. Overview of the automated RF WLT.
Therefore a Known Good Die RF Wafer Level Test (WLT) is an imperative to maintain the complex module performance, and hence, the assembly line module yield.
The semiconductor test manufacturing is used to performing RF wafer level tests of billions of power amplifiers, low noise amplifiers, cellular or connectivity transceivers below the 6 GHz carrier frequency, and most critically, a measurement bandwidth of less than 250 MHz. However, above this frequency, very few industrial ATE are available in high volume manufacturing. It is also true because RF ATE means high throughput and low test time in narrow band, single tone scalar measurement. However, quad channel 32Gbps TIAs testing requires measuring the s-parameters, namely Gain and Output Return Loss from 100MHz up to 40 GHz, to calculate out the trans-impedance, but also group delay and in some particular application the Total Harmonic Distortion (THD) to evaluate the linearity of the devices. On top of this frequency domain testing, parametric test of the power supply is extremely important to reduce the impact of the Input Referred Noise on the RF measurement.
All in one, it is far from a traditional production test practice, and very close to a characterization set of frequency tests using a highly automated rack of discrete instruments. Indeed, ATE capital cost per unit cannot be reduced with parallel testing and test times are way above traditional RF connectivity or cellular devices ones. This observation poses the question of the millimeter wave radiofrequency test challenges to sustain such a volume test operation.
Brief introduction to MMW test challenges: a 25g quad-TIA case study
Challenge 1: the traditional 3 rules of measurement.
Each measurement performed in the production RF wafer level test suffers from the well known systematic, random and drifting errors. Regarding RF 40 GHz WLT, the systematic measurement errors in forward and reverse testing of our 25G 4-channels TIA has a lot to do with the test cell mechanical and electrical design. Among others, the directivity and cross-talk errors due to the cabling custom set-up for the GSG probe and supplies. The source and load impedance mismatches as well as reflection and transmission tracking errors can then only be limited by a very thorough Short-Open-Load-Through (SOLT) calibration and this at every incoming lot to avoid lot to lot variation over time.
The random error component is directly related to the capability of managing very long test time and multiple touch-downs over a single wafer. In our case of the 25G 4-channel TIA, the device can remain tested over minutes at hot and cold temperature insertion. In this case device self-heating while probing as well as two necessary touch-downs per die to measure the s-parameter of the 4 differential channels are clearly the first detractors. They are followed by the VNA internal thermal noise in time. Trade-off are always possible to mitigate the random error, such as decreasing the IF bandwidth to enhance accuracy or averaging on different sweeps, with both solutions causing a longer test time.
The drifting error in our 40 GHz WLT is mainly dependent upon the strict calibration process and mechanical stability, thermal control at -/+ 5°C of the test cell.
Challenge 2: A key thorough probing and over travel control.
As already explained, two touch-downs with the RF GSG and DC probes are necessary along the whole device testing. It mainly requires carefully monitoring the contact resistance along the test, but also between insertions to avoid offset in RF measurements. In addition, DC probe pads are probed twice which increases the impact of the die pad scrub form or bump tip mark on bonding yield, but also affects the input referred noise injected between insertions, hence the TIA channel to channel performance correlation and matching.
Such a two insertion per die approach could be mitigated by performing a single touch-down on the 4 channel. If the capital cost increased by adding equipments can be discussed, the probing would have to move from wedge probes to membrane probe card well known for their RF performances to improve isolation and probe congestion. However, the inter-channel cross-talk when simultaneously sourcing the 4 inputs is a fairly complex issue to handle and cause very difficult repeatable tests.
In a nutshell, analog high speed communication devices are far from fitting into a standard, high volume manufacturing test process with a well-established set of best-known practices. However the volume of 100G optical ports is surging in long haul and metro aggregation routers and transponders. This surge is not likely to abate with the booming of the IoT, and within the supply chain semiconductor manufacturing test has to bridge the gap between what was considered as a bench top characterization and what volume test production worthy demands at the appropriate cost. This is the challenge Presto Engineering has taken up by becoming the leader in the optical communication electronics device production testing for the 40G/100GB Ethernet market. It required a thorough learning curve and development of dedicated methods, and it is now a fully sustainable production operation, ready to support the rapid growth at the eve of the 400G Ethernet ratification and the silicon photonic roll-out.