Next-Generation Semiconductor Technologies Enable Smart Sensors for Mobile Products



Advanced technologies help smart sensors achieve the sensing, signal conditioning and control functions required for their efficient integration into mobile devices.

Introduction
Modern mobile devices such as smartphones are becoming smarter and more useful thanks to the integration of smart sensors. Compared to early phones which only included a few sensors such as an image sensor (camera) and a microphone [1,2], today’s cell phones include many additional sensors such as ambient light (ALS) and proximity (PROX) sensors, gesture recognition sensors, accelerometers and gyroscopes, magnetic (Hall and e-compass) sensors, temperature and humidity sensors, etc. To integrate these sensors while minimizing size, weight and power consumption, new advanced semiconductor technologies must be leveraged.

Product developers have access to multiple technologies with different minimum feature size, either through their internal factories or through foundry service providers. For digital-intensive products, the choice is relatively simple: follow the well-known “Moore’s Law” [3] and use technologies with the smallest feature size (down to 22nm in production today [3]). For smart sensor products, which combine digital, analog and mixed-signal circuits with a sensing element, the choice is not trivial, since smaller may not necessarily be better.

In this article, we compare the existing and popular 0.35 and 0.25 micron technologies, to new advanced processes with features size of 0.18 micron and below, to determine the best technology platform for smart sensor products.

Smartphones Require Smart Sensors…in High Volumes
The volume production of mobile devices such as smartphones has grown at a compound annular rate of more than 60% from 2009 to 2012 [4]. Over the past five years, the number of sensors integrated in mobile devices has more than doubled, reaching approximately 12 sensors for phones manufactured in 2013, as shown in Figure 1. The volume growth combined with the increased integration of new sensors is driving the need for very high-volume sensor manufacturing.

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Figure 1: Sensors in a typical smartphone

To support volumes in excess of one hundred million units (per sensor type), and to not disrupt the supply chain (by running out of capacity for example), the “right” large-scale semiconductor manufacturing approach must be employed. In semiconductor manufacturing, there are two important initial parameters to determine: the diameter of the silicon wafer and minimum dimension of the patterns to be printed on the silicon wafer. Regarding the wafer diameter, 300 mm is the most popular diameter for digital-intensive products [5], but for analog and smart sensor applications, 200mm is in fact preferable [6]. In terms of feature size, most of today’s high-volume sensors are based on technologies with 0.35 and 0.25 micron minimum feature size. Smaller features than 0.25 micron must be considered in order to minimize the die size and wafer volumes needed to support the growing demand for smart sensors.

The Right Platform Technology: 0.18 Micron or 0.25 Micron?
Many platform technologies are available to sensor designers and manufacturers. The most popular platform is based on 0.35 micron CMOS, available on 150mm and 200mm wafers, with a logic gate density of >25K gates/mm2 and a significant manufacturing (captive and foundry) base. The second most popular platform is based on 0.25 micron CMOS and features a 2X logic density increase over 0.35 micron, with a >50Kgates/mm2 logic density. Both of these technologies are not ideal options for current mobile phone and tablet platforms: standard 1.8V I2C interface is not supported without additional processing steps, power dissipation is excessive for mobile applications and the resulting die size becomes excessively large resulting in high cost. In addition, 0.25 micron based technologies are not available in every foundries or captive fabs.

A much better technology choice to minimize cost, minimize power and maximize performance is to use 0.18 micron-based CMOS technologies; 0.18 micron is much more competitive than 0.25 micron and larger geometries.

  • 0.18 micron technologies achieve a >2X increase in logic density compared to 0.25um CMOS: >110K gates/mm2 compared to >50K gates/mm2 because of the smaller feature size achieved by more advanced photo-lithography.
  • 0.18 micron technologies can operate at a reduced supply voltage of 1.8V compared to 2.5V for 0.25 micron or 3.3V for 0.35 micron CMOS. The lower operating voltage reduces the power dissipation and enables significant device shrink
  • 0.18 micron technologies with single 1.8V operating voltage can have lower manufacturing cost. For example, the same 1.8V devices can be used for both core logic and input, output and interface (I/Os). Most technologies with larger geometries must integrate low and medium voltage transistors on the same die, which requires additional processing steps.
  • The power consumption of circuits designed using 0.18 micron technologies can be significantly reduced when compared to 0.35 or 0.25 micron designs. For example, a typical 0.18 micron 1.8V-operating digital circuit may consume only 30 [nW/gate/MHz], which results in a >10X (0.18 versus 0.35) and >3X (0.18 versus 0.25) reduction in the power dissipated during switching.

Based on the above, 0.18 micron technologies are much superior to 0.35 or 0.25 micron processes, but what about technologies with feature size less than 0.18 microns?

Are Geometries Smaller than 0.18 Micron Better for Smart Sensors?
Technologies with feature size below 0.18 micron are ideal for digital intensive applications as mentioned earlier, but how efficient are they for smart sensor products? Since smart sensors integrate in one die, digital as well as “non-digital” circuitry, calculations which take into account the area of major functional blocks are required in order to compare the technology options. The information necessary for these calculations, such as the normalized wafer price [7] and digital density as a function of technology node, is listed in Table 1.

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Two smart sensor products with different digital content have been considered. The first sensor product has a digital content which takes up 50% of the die area. The remaining area is used by the following blocks: 20% for the sensing element, 20% for the analog signal processing circuitry and 10% for the input/output (I/O) and connection pads. The second product has a digital content which requires 65% of the die area, with 12% of the remaining area taken up by the sensor, 13% by the analog circuitry and 10% by the I/O. The die size of these two smart sensors is calculated for the different technology nodes, by assuming an area shrink of the digital portion of the die, based on the gate densities listed in Table 1. In the calculations, the area of the sensing element and I/O is assumed not changed, while the area of the analog signal conditioning circuitry is estimated to reduce by 5% when changing from one node to the next smaller node. The die cost is determined by multiplying the normalized wafer price of Table 1, with the calculated die area.

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Figure 2: Normalized die cost, as a function of technology node.

Figure 2 shows that a minimum die cost is obtained when 0.18 micron technologies are utilized, for both product examples. For nodes larger than 0.18 microns, the lower wafer cost does not compensate the increase in die size. For nodes smaller than 0.18 microns, the die size reduction does not compensate the increase in wafer cost.

Integration of Smart Sensors
The integration of smart sensors with other functions requires careful selection of key process modules. Standard CMOS technologies for example, cannot be used as-is. There are a number of enhancements which must be implemented to integrate sensors and to ensure adequate operation, including improved isolation, noise reduction and optimized sensor modules.

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Figure 3: Cross-section view of an optimized 20 micron Deep Trench Isolation (DTI) with Air-Gap, for improved performance (courtesy of MagnaChip Semiconductor)

Integrating the smart sensor next to sensitive circuitry requires improved device isolation. Typical isolation approaches include: Deep well junction isolation, deep trench isolation (DTI) and silicon on insulator (SOI) substrates. The approach with the best cost-performance trade-off is DTI. An example of a DTI structure is shown in Figure 3.

  • DTI is compatible with standard low-cost wafers (SOI wafers offer the best isolation, but they are very expensive, typically >6X the cost of standard silicon wafers)
  • DTI improves the packing density of medium and high-voltage circuits compared to junction isolation (DTI does not suffer from lateral diffusion and depletion regions of deep well junction isolation approaches)
  • DTI improves switching performance by reducing the parasitic capacitance of the isolation region between devices (air gap DTI for example, results in a much lower sidewall capacitance than junction isolation)
  • DTI requires silicon trench etching, which is a commonly available process module (used in DRAM manufacturing for example)

A second critical requirement is the need for low-noise analog circuitry to convert the output of the smart sensor to appropriate electrical signals. Low-noise CMOS can be achieved by special processing to improve the sensitivity of the signal-conditioning circuitry. Figure 3 shows an example of an N-channel low-voltage MOSFET with and without modifications to reduce the noise level, showing a 50% improvement in the voltage noise.

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Figure 4: Svg (input referred noise power) is plotted versus frequency for the same 1.8V NMOS with and without the low-noise module (courtesy of MagnaChip Semiconductor). A 1/f noise reduction of 50% is achieved.

A third requirement relates to the integration of the sensor element. Smart sensors which are optimized for their specific application require the addition of specialized process modules. Examples of sensor modules include:

  • Optical sensors require the addition of organic and/or dielectric optical filters which are deposited and patterned directly over PN junction photo-diodes integrated on wafers.
  • eCompass sensors require the deposition and patterning of magnetic materials.
  • Gyroscopes and accelerometers require the use of micro-machining to form balanced beams and other structures, using microelectromechanical systems (MEMS) techniques.
  • Humidity sensors require the deposition of moisture sensitive materials.

These specialized process modules are available in high-volume manufacturing facilities: captive manufacturing facilities, foundries or available from vendors who specialize in “post processing” of completed wafers.

Conclusions
The demand for smart sensors, fueled by the explosive growth of smartphones throughout the world, requires the use of new advanced technologies in order to realize all of the sensing, signal conditioning and control functions required for their efficient integration.

A wide range of technology nodes have been considered, and the 0.18 micron node has been found to be the most efficient in terms of cost, size and power dissipation. Smart sensors based on 0.18 micron technologies are expected to ramp to high volumes in the near future.

References

[1] http://www.businessinsider.com/complete-visual-history-of-cell-phones-2011-5?op=1
[2] http://en.wikipedia.org/wiki/Camera_phone
[3] http://en.wikipedia.org/wiki/Moore%27s_law, and http://en.wikipedia.org/wiki/22_nanometer
[4] Gartner, “Semiconductor Forecast Database, Worldwide, 2Q13 Update" 4 June 2013
[5] http://www.radio-electronics.com/news/electronics-manufacture/ic-insights-installed-300mm-wafer-capacity-3237

 


herbert_francois

Dr. François Hébert joined MagnaChip in 2012. As vice president of engineering, he supports the definition and development of advanced technologies including smart sensors, BCD (to 800V) for analog and power applications, SOI and new materials for RF and high-voltage. Prior to joining MagnaChip, François held technology leadership and management positions at leading analog, power and mixed-signal semiconductor companies, including: Intersil, Alpha and Omega, Fultec (now Bourns), Linear Technology, Spectrian (now Cree), National Semiconductor (now TI) and Avantek (now Avago). François received a Ph.D. in electrical engineering from the University of Waterloo in Ontario, Canada. He has invented or co-invented more than 120 granted US patents.

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