LPDDR4: Meeting the Power Neutrality Challenge in Mobile Handsets



JEDEC has defined the fourth generation of low-power DDR (LPDDR) that can help developers achieve power neutrality in handset applications, as well as improving performance and cost.

As new capabilities and functionality are added to mobile handsets, they become more compute-intensive. For example, in higher-resolution cameras and screens, CPUs must perform more work and memory devices must move more data, faster. Consider ultra-high-definition (UHD) video capture, which is currently a differentiating feature in high-end handsets. To support UHD video, a 64-bit system requires 25.2 GB/s of peak bandwidth.
On the surface, UHD may seem to be of limited value—after all, handsets don’t have 4K displays and, as yet, few users take advantage of features like streaming UHD video to a living room TV.
UHD becomes more compelling when users want to capture moments in real time, where the most immediately available camera is often on a handset. These moments are then shared across the Internet, sometimes viewed on devices like tablets, laptops and desktops that have UHD resolution-capable screens. No one wants their priceless moments to be low-quality or pixelated. Thus, even though a handset does not directly display UHD, many users consider it important that their devices are capable of capturing, and therefore processing, that number of pixels.

The Power Neutrality Challenge
Next-generation handsets must perform more work than earlier-generation devices without decreasing battery life. Users have come to expect extended battery life and demand that the next-generation handsets maintain the same battery life (at a minimum) as their predecessors—even when they have more/improved functionality.
This concept, called “power neutrality,” is a major design consideration for mobile devices. For a next-generation device to perform more work using the same amount of power, the energy required per bit processed must be cut in half across the entire system. This can be extremely difficult given that handsets depend on multiple technologies that are not advancing quickly enough to keep pace with power neutrality.
Specifically, the voltage rail has not dropped significantly—nor is battery capacity growing fast enough. The form factor for handsets is also fairly stable (with some exceptions), limiting overall battery size. Furthermore, the thermal design point (TDP) or envelope—which is the maximum amount of heat these systems can safely dissipate—is limited to 5 watts. Because the user is the final heat sink in many cases, these systems simply cannot take on more heat. Because there is nothing on the horizon to suggest that these technologies are changing any time soon, even greater efficiency is required from the other parts of the system.

LPDDR4: A More Power-Efficient Memory Solution
In today’s handsets, memory devices consume up to 30% of system power in standby modes. Thus, efficiencies in memory management play a substantial role in enabling manufacturers to achieve power neutrality.
To help developers improve a system’s energy consumption per bit processed (see Figure 1), JEDEC has defined the fourth generation of low-power DDR (LPDDR). LPDDR4 provides more than just a speed upgrade from LPDDR3; it’s an evolutionary step up thanks to enhanced functionality that can help developers achieve power neutrality in handset applications. LPDDR4 also doubles bandwidth performance, provides a low pin-count package, is backward compatible with previous generations of LPDDR and enables competitive pricing.

fig01
Figure 1: Mobile DRAM power requirements include active and stand-by power.

The LPDDR4 standard introduces several major architectural changes that are specifically designed to reduce the energy required per bit (see Figure 2):

  • 2-Channel x 8-Bank Architecture: The internal LPDDR4 architecture contains two 16-bit channels (instead of one 32-bit channel), which reduces the effects of parasitic capacitance and results in lower active currents for READ and WRITE operations.
  • 2K Page Size: The reduced DRAM page size (from 4K to 2K) decreases the amount of current required to activate a page when opened.
  • 1.1V Supply Voltage: The reduced supply voltage (from 1.2V to 1.1V) provides a 20% decrease in switching power and approximately 10% savings in static power.
  • Advanced LVSTL Interface: The low-voltage swing (VOH) of LPDDR4’s low-voltage swing-terminated logic (LVSTL) interface saves more than 50% power when switching I/O compared to LPDDR3.
Untitled-2
Figure 2: LPDDR4 is architected to meet the power, bandwidth, packaging, cost and compatibility requirements of the world’s most advanced mobile systems.

The LVSTL Advantage
Low-voltage swing-terminated logic (LVSTL) is a significant enhancement to mobile memory technology. The LPDDR4 interface supports a programmable voltage level that divides the power supply rail for I/O by either 3.0 or 2.5. The 3.0 mode is intended for systems with better channel design and/or less loading. For more heavily loaded systems, or those with more channel losses, the 2.5 mode can be used to adjust power efficiency to increase signal integrity. This enables developers to balance cost, signal integrity and power. For example, a developer could select the 2.5 mode and use a lower-quality PCB material to reduce system cost.
LVSTL also provides a variety of termination settings, ranging from 40 ohm to 240 ohm. In general, the stronger the termination (40 ohm), the better the signal eye across the channel. However, stronger termination also consumes more power. By adjusting termination settings, developers can tune systems for a variety of configurations, such as stronger termination for a lower-end handset. This flexibility also simplifies design because developers can initially set systems to the lowest power setting (240 ohm) and increase the termination level if greater signal integrity is required.

Simplified Design Process
It is important to note that LPDDR4 is not a drop-in replacement for LPDDR3. Systems need to leverage LPDDR4’s power-saving features to fully optimize power efficiency. To simplify design for developers, memory suppliers like Micron have partnered with industry-leading controller manufacturers to provide optimized LPDDR4 memory, which enables developers to focus engineering resources on their own value-added innovations. As one of the creators of the LPDDR4 standard, Micron has the experience to help developers become familiar with the new memory technology as well as design custom solutions using it.

Memory Is No Longer a Bottleneck
Because LPDDR4 provides 2X the bandwidth (up to 34 GB/s) of LPDDR3 while using less energy per bit, memory is no longer a bottleneck for UHD and other compute-intensive applications in mobile devices. LPDDR4’s power efficiency enables it to be an effective enabler of UHD technology, and thanks to its flexible implementation, LPDDR4 also gives developers more options for balancing signal integrity and power efficiency and, consequently, more control over cost versus power efficiency.
LPDDR4 provides more than just stellar bandwidth, improved power efficiency and power neutrality; developers can rely on packaging with lower pin counts for greater board density, low costs and backwards compatibility to previous generations of LPDDR—all without compromising performance.
The open design of today’s mobile handsets mean they should be able to do everything we want them to. With LPDDR4, they can.


dan_skinnerDan Skinner joined Micron in 1989 as a product engineer in the Memory Application Group, and has since worked with DRAM, SRAM, flash memory and TCAM products. Throughout his career with Micron, Skinner has held management positions in engineering and marketing, most recently managing the CellularRAM™, Mobile SDRAM and RLDRAM™ product lines. He was appointed to his current position in 2006. Skinner holds a bachelor of science degree in electrical engineering from the University of Colorado and MBA from the Kellogg School of Management at Northwestern University.

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