Next Generation Memory: A Competitive Weapon for Mobile Devices



Has a solution emerged which balances cost/performance, endurance and low power?

The entire memory industry is investing heavily in next-generation memory technologies, as it now is very clear that customer demand is enormous and still unmet. Mobile manufacturers in particular are looking for the next big competitive advantage, and all signs point to new memory technologies as the most powerful choice. The traditional memories, DRAM and NAND, are falling off Moore’s law and can’t continue doubling in density every two years. Clearly a new memory technology is needed to pick up where these two technologies are leaving off.

As engineers struggle to figure out how to get the next-generation memory technology to be 40-50% smaller, the finance teams are looking at the costs associated with the new technologies, such as 3D NAND, and are very concerned with their ROIs, given the high cost of technology conversions. DRAM and NAND flash memory represent a $45B and $35B market respectively. Figure 1 shows how the growing complexity is having an impact.

 Figure 1:  Concerns associated with traditional memories and shrinking geometries. Source: Micron Analyst Presentation, February ‘15

Figure 1: Concerns associated with traditional memories and shrinking geometries. Source: Micron Analyst Presentation, February ‘15

Figure 2:  Memory Hierarchy. Courtesy IBM Corporation.

Figure 2: Memory Hierarchy. Courtesy IBM Corporation.

If a new memory technology is not lower cost than NAND, then the other memory technology it must compete with is DRAM. While DRAM is a much easier target from a cost standpoint, architecturally the bar is high, as the memory technology must “talk” directly to the CPU. If one can develop a “drop-in DRAM-compatible memory” that is lower cost, one can compete directly with DRAM, as this solution requires no changes to the CPU. Again, much easier said than done, as the new memory must be fast and low power enough to be compatible with the DDR standards. Because NAND is a highly cost-optimized, high volume technology, it is extremely difficult, if not impossible, for any new technology to be lower cost than NAND right out of the gate.

To become cost-competitive with NAND requires selling substantial volumes to get down the cost curve, but customers will not buy if it is more expensive, leading to a deadly catch-22 if the new technology is trying to compete with NAND right away. Therefore, any new memory technology must initially compete with DRAM in order to succeed. Only one with the right balance of cost, performance and reliability can ultimately win out.

What is rarely discussed is the value proposition of a new memory technology and where it will likely fit in the memory hierarchy. Let’s look at the compelling value proposition for storage class memory replacing DRAM + NAND, specifically in mobile applications.

Memory Hierarchy
In the late 2000s, IBM coined the term “storage class memory” (SCM). It was used to generically describe a class of memory that sat, hierarchically, between DRAM and storage (Figure 2). As you can see, in 1980 memory hierarchy consisted of RAM and disk. DRAM was volatile and called “working memory” and storage was non-volatile. With the introduction of solid-state drives (SSDs) in the late 2000s, the depiction shows SSDs slipping in between RAM and disk.

The 2013 view shows SCM sitting between RAM and disk. While the depiction is admirable and correct from a cost and performance standpoint, there are several issues. First, the advent of SCM does not negate the need for SSD unless the SCM technology is lower cost than NAND flash memory, which is highly unlikely for quite a while for the reasons discussed above. Second, if it isn’t lower cost than SSD, in order to be of value it cannot serve as mass storage, it needs to either displace some DRAM or directly augment DRAM as another level of cache. The amount of DRAM it can displace will be a function of the attributes highlighted above, such as cost, power, performance and endurance.

Historical View of Mobile Architecture
Despite the SCM concept being introduced by IBM in the mid 2000s, one doesn’t need to go back that far to get a view of “SCM” in action. Let’s take a historical look at mobile architectures, focusing mainly on the cellular phone in the 1990s to understand the value proposition of SCM.

During this time frame, the predominant memory technology used in cellular phones was NOR. At its peak, it was an approximately eight billion-dollar market and could easily fit the definition of a storage class memory. That is, it was directly connected to the CPU, lower cost per bit than DRAM + NAND— at the desired capacities, and was able to execute code and store data with non-volatile characteristics.

Crucial for any SCM is its ability to execute code and store information with some level of permanence. NOR did all of these well with its architecture coined “XIP,” or “execute in place.” This stems from the ability for the storage device, the NOR, to store the code and data and execute from it directly to the CPU. However, an alternative architecture ultimately won out, which was called “store and download” or “SND.” This architecture consisted of DRAM and NAND whereby the code and data were stored in NAND, copied to DRAM upon power up, and executed to the CPU out of DRAM. NOR ultimately lost to DRAM + NAND because it could no longer scale, which translated into higher costs and lower capacities than DRAM, so for this reason the SND architecture prevailed.

The goal is that a next-generation memory will finally provide the performance, cost point, and value proposition to make the architectural conversion to XIP a reality, benefitting the end-user through the increased speed and reduced power consumption that XIP has always promised.

Requirements for Next-Generation Memory
As with any memory technology, each has its own unique value set. Table 1 summarizes the incumbent technology values.

”

Table 1. DRAM and NAND are almost the opposite of each other and paint the two ends of the spectrum. All next-generation technologies fit somewhere in the middle.

  • Performance: Having a next-generation memory technology that provides DRAM-like performance is key. The impact of SCM with DRAM-like performance to the end user is two-fold: (1) “instant on” performance and (2) code that does not consume storage gigabytes.
  • Power: Having a non-volatile executable memory will increase battery life by a noticeable amount. In a patent application by Intel (Patent 20130283079), the company stated that replacing DRAM in a laptop with an SCM has the potential to increase standby power from days to a few hundred days.
  • Endurance: As noted above, DRAM has “infinite” endurance while NAND is fairly limited. 2D NAND is in the 1-3K write cycle range, while 3D promises to deliver 40-50K write cycles. Having a next-generation memory technology that is infinite, like DRAM, is highly desired. While the desire is to have infinite endurance, simply because not thinking about it is always easier, lower endurance levels can certainly be managed around for many applications. The closer a technology gets to infinite, the easier that management becomes.
  • Cost: Having a next-generation technology that is lower cost than DRAM + non-volatile storage is imperative. If there’s a “drop-in” compatible technology that’s lower cost than DRAM, it will win. In the height of NOR, the reality was NOR was lower cost than DRAM + NAND. It took a tremendous amount of education in the industry to make the point that NOR never competed with NAND alone, it competed with DRAM + NAND. This is an extremely important concept, as it will become center stage once again as the industry moves to next-generation memory solutions and influences the choice of solution.

Who Will Win?
Many technologies in development today aim to be the next big memory technology to replace DRAM and flash. However, not all will win because they don’t have the right balance of cost/performance, endurance and low power. One of the most promising technologies, developed by Nantero, Inc., is NRAM (Table 2).

”

Table 2: How NRAM compares to both DRAM and NAND.

  • Performance: With a DDR interface, latency of ~50ns, and a bandwidth of 2133MT/s, NRAM is by far the highest performance next-generation memory technology today. No other technology proposed offers this level of DRAM-like performance.
  • Power: It is nonvolatile, so unlike with DRAM, refresh is not required and hence standby power is much, much lower.
  • Endurance: While it is believed to fundamentally have infinite write capability, like DRAM, its first instantiation will offer 109, which is more than enough for many demanding applications.
  • Cost: Less than DRAM.

Plan for the Future Today
Next generation memory provides the opportunity to meet consumer expectations of: (1) higher performance and much less stand-by power on mobile devices, and (2) true instant-on for laptops. The time for thinking about these technologies is now while they are being developed. Users of memory need to start planning the required changes to both architecture and software to take advantage of them. Engineering and procurement teams must balance the value of cost, power, reliability, and ease of use to make the best decisions.

The stakes are high. This will create a competitive advantage for OEMs as they can now for the first time use memory technology to differentiate their products and create competitive advantage leading to enhanced revenue growth and market share gain.

For a more thorough discussion of how memory is the next big opportunity for differentiated mobile devices, a white paper on this topic by the author is available.


ed-doller-smallEd Doller is President of Doller Consulting. Doller is a semiconductor memory and storage industry expert with over 31 years experience. He was most recently a corporate officer at Micron Technology where he held the role of VP & Chief Strategist of the NAND Solutions Group. Prior to that, he served with Micron as VP & GM Enterprise Storage and also as VP & Chief Memory Systems Architect. He joined Micron in 2010 via the Numonyx acquisition where he served as VP & Chief Technology Officer after its formation in 2008. Before Numonyx, Doller spent 15 years at Intel in the Flash memory group where he was appointed its Chief Technology Officer in 2004. Prior to Intel, he spent 9 years at IBM in East Fishkill, N.Y. and held several key positions all in advanced semiconductor memories. Doller earned a Bachelor of Science degree in computer engineering from Purdue University. He holds multiple patents, is a co-author of the IEEE floating gate standard, and is a frequent keynote speaker at memory conferences.

Share and Enjoy:
  • Digg
  • Sphinn
  • del.icio.us
  • Facebook
  • Mixx
  • Google
  • TwitThis

Tags: