Power7 Performance Guide v 1.0.2

Power7 Performance Guide v 1.0.2

White Paper on PowerEN™

> A2 Core, full 64 bit based on Power Architecture® technology and support Power ISA 2.06

> 2.3GHz 45nm SOI with 16 cores and 64 Threads

> Low power, highly scalable design - 25-75W chip at full frequency

IBM announced a new IBM PowerEN™ as a new 64 bit architecture based on Power Architecture® technology and support Power ISA 2.06 to address the converging market between the network and servers.

Power.org Q1 2010 Newsletter

Power.org Q1 2010 Newsletter

Deploying Ruggedized Systems in Unmanned Military Vehicles for Advanced Air-Sea-Land Applications

An overview of the challenges, constraints & opportunities in the military’s most demanding environments – Part 1 describes the escalating trend toward the use of advanced unmanned vehicle platforms as key tactical elements within overall military reconnaissance and war-fighting strategies. Part 2 provides a more detailed exploration of the specific implementation methodologies and issues that must be addressed in the creation of high-performance, ruggedized systems to meet the needs of these ultra-demanding deployment environments.

Delivering Synthesizable Verification IP for Test Benches

High-level verification languages and environments such as e/Specman, Vera and now SystemVerilog, as used in VMM or OVM, may be the state-of-the-art for writing test bench IP, but they are not synthesizable for developing models, transactors and test benches to run in FPGAs for emulation and prototyping. So engineers wishing to move verification assets onto FPGAs have been designing with RTL, the same old slow, resource-intensive and error-prone way.

But now, with the introduction of modern high-level languages for synthesizable verification IP, engineers can design test benches, models and transactors at a high level of abstraction and with extreme reuse, but they can also synthesize them onto FPGAs – and they can do this as easily as they do today in simulation-only verification environments. Imagine running your test benches, models and transactors at tens of MHz.

This White Paper outlines important attributes of, and the applications for, modern high-level synthesizable verification environments. Using the example of a test bench for an Ethernet MAC, the paper compares the implementation of a synthesizable test bench done with Bluespec’s BSV with a non-synthesizable reference test bench done with SystemVerilog VMM – and it demonstrates that a synthesizable test bench can be implemented with fewer lines of code than using state-of-the-art SystemVerilog.

Creating Multi-Time-Domain ATE Test Programs for SOC Device Designs

Creating Multi-Time-Domain ATE Test Programs for SOC Device Designs [company]

Multicore: Bare Metal Speed, AMP Scalability, SMP Simplicity in One RTOS

Moore’s law does still hold, but processor vendors are rapidly turning to use the additional transistors to create more cores on the same die instead of increasing frequency since this not only gives more chip performance but also decreases the power consumption (watt/mips). This paper starts by describing the widely accepted multiprocessing software design models, and some of their benefits and drawbacks.

MontaVista Linux 6

Description: This short 6 minute video will walk you through building a distribution using MontaVista Linux 6. You'll see how to use the new MontaVista Integration Platform to download the source and build a complete embedded Linux distribution in less than an hour.

UTM Security Appliance Solution Utilizes QorIQ P1020 and VortiQA Software for Enterprise Equipment

This demo shows the UTM security appliance solution featuring the Power Architecture®-based QorIQ P1020 processor and VortiQa software for enterprise equipment. Watch this video here:

EtherCAT on Safety-Certified INTEGRITY OS Demo

This demo features an Acontis / IXXAT EtherCAT master run on the QorIQ P2020 multicore processor and Green Hills' IEC 61508 SIL3 certified Integrity® OS. Watch this video here:

Adax Packet Processing Solutions for NGN, IMS & LTE networks

The transition of telecom's core infrastructure transport network from deterministic circuit-based management to a packet-based architecture is well underway and Next Generation Networks are required to deliver packet-based and circuit-based services. Adax provides a full array of packet processing products along with its expertise in signaling reliability and performance to bear on this problem of carrier grade IP networks.

Tangible Learning Cubes for WIMAX

This video described a tangible cubes game designed to teach undergraduate networking students about signal propagation in WIMAX networks. The hardware is based on a Zigbee network and was designed by Dr. Imran A. Zualkernan and his students Jamshed, Moataz and Arsalan at the American University of Sharjah in the UAE.

100 Gbps Ethernet - Interop Tokyo 2010

At Interop Tokyo 2010, NTT Communications unveiled a 100 Gbps Ethernet network, fast enough to send the data of Blu-Ray disc in two seconds.

The Radisys COM Express Family of Extended Temp Products

Product Line Manager, Lorraine Orcino, introduces the Radisys COM Express family of extended temp products