USB 3.0 – Protocol Verification at SuperSpeed!



USB 3.0 early adopters will begin testing the next-generation peripheral interconnect (known as SuperSpeed USB) later this year. Promising ten times the speed of USB 2.0 and backward compatibility with legacy USB devices, product verification teams testing these chipsets will face numerous hurdles along the way. Early USB 3.0 developers cite the shortage of native SuperSpeed PHY chips as well as sophisticated physical layer features including high speed signaling, dynamic equalization, and power management as key challenges for their product validation efforts.

Fast Lock Times

USB 3.0 shares many physical layer characteristics with PCI Express® 2.0 including 5 Gbps signaling and an embedded clock which requires a PLL for data recovery. USB 3.0 introduces a new connector design with cable lengths to 3m. Attenuation on the 5 GHz serial lines is considerable and receivers operate on very small margins. In addition, USB 3.0 demands fast transition from electrical idle to the active state. To provide accurate data capture, analysis tools must tap these 5 GHz signal while sitting in line and extract clock timing by phase locking to the electrical transitions. The analyzer SERDES must detect electrical idle and achieve bit lock to “follow” each link state transition. Any delay in lock on the signal can cause the analyzer to miss data. If the analyzer is unable to stay synchronized with the TX / RX pair, the system will record “garbage” in the trace.

Dynamic Equalization

It’s anticipated that most USB 3.0 devices will use dynamic receiver equalization to overcome signal loss common when operating at 5 GHz frequencies. SuperSpeed PHYs will cycle through special equalization functions during link training and adjust the receiver eye to minimize the effects of dielectric loss and cross-talk. To ensure link synchronization, the SERDES on the analyzer must also tolerate these adjustments.

PHY Availability

For early USB 3.0 developers, testing challenges are aggravated by the scarcity of 3.0 PHYs. In some cases, vendors will use prototype PHYs on development platforms prior to integrating the analog block into an ASIC. To enable early testing, these prototype PHYs are also used on the test equipment. But incorporating these early stage development PHYs within an analyzer probe may yield poor interoperability when testing with production silicon. Fortunately, after huge investments in modeling with PCI Express, test vendors like LeCroy Corporation have developed alternate analog front-end (AFE) probing schemes for 5 Gbps signaling that reduce the reliance on test PHYs.

Power Management

The USB 3.0 specification defines aggressive power management strategies to extend battery life and reduce power consumption. When a SuperSpeed device exits electrical idle (U1 transition to U0), it issues the Low Frequency Periodic Signaling (LFPS) handshake and moves through the required Recovery and Link Training states. The USB 3.0 specification currently defines a rigid exit latency of <1us from U1 to U0 power states. As with initial link training, the analyzer front-end must detect each state during these frequent power save modes. Any delay in lock when exiting electrical idle can cause the analyzer to lose synchronization with the DUTs.

Introducing LeCroy Voyager USB 2.0 & 3.0 Verification System

The Voyager M3 is the world’s first SuperSpeed USB analyzer / exerciser system for verifying USB 2.0 & 3.0 chip sets. The Voyager front-end leverages custom circuitry from LeCroy’s 5 Gbps PCI Express Gen2 analyzer to provide fast locking and uncompromised accuracy for SuperSpeed recording. Fully compatible with spread spectrum clocking (SSC), data scrambling (LFSR), and dynamic equalization, the analyzer can sit in the data path and seamlessly recover from electrical idle while accurately showing all bus and power state transitions. The system includes both SuperSpeed connectors and SMA differential Input/Output lines as an alternate physical interface for taping between early development boards. Available as an integrated analyzer / exerciser, the system can operate with fractional clock rates or use an external clock source with timing as low as 10 KHz. The Voyager utilizes the legendary CATC Trace which is the industry’s de facto standard display for USB 2.0 protocol analysis. Fortunately for many of the 3.0 verification projects, the protocol experts at LeCroy have already cleared the 5 Gbps probing hurdle for SuperSpeed USB.

 

Contact Information

Teledyne LeCroy

700 Chestnut Ridge Rd
Chestnut Ridge, NY, 10977
USA

toll-free: 800-553-2769
www.teledynelecroy.com

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