Today’s IP choices for the Universal Serial Bus (USB) cover many different types of interfaces for a wide variety of applications-including portable consumer products. Power consumption and small form factors are key issues. SoC designers must also consider new requirements imposed by smaller technology nodes, especially for the USB PHY. As the most successful connectivity standard in history, USB has expanded from connecting PCs and PC peripherals to flash storage, digital imaging, audio and video, wireless, automotive, and now to tremendous growth in mobile phones. A force behind this growth are the ongoing enhancements to the USB standard, including the PictBridge specification that supports direct connections between printers and digital cameras and most recently, the High Speed Inter-Chip (HSIC) and Link Power Management (LPM) standards that lower power, area and enable chip-to-chip connectivity with USB. We will also begin to see the emergence of products based upon the USB 3.0 standard, which can deliver over 10 times the speed of today’s USB 2.0 connection.

Issues such as power consumption and small form factors in consumer products drive many of the key USB challenges for the design community today. The recent USB High Speed Inter-Chip (HSIC) standard makes it easier to interconnect other functionality that has been partitioned into multiple chips. USB HSIC offers an easy way to connect many different types of functions in a system. Since USB is already used extensively to connect products using the traditional USB cable, it is a good choice to move inside the system and act as a high speed chip to chip interface. For example, USB HSIC can be used to connect an embedded webcam, GPS, or Wifi chip to an applications processor within a smart phone or small form- factor embedded PC. Significant time and cost is saved because USB drivers and firmware that work with traditional USB 2.0 systems can be reused in USB HSIC applications.

Figure 1: USB High Speed Inter-chip Only Requires Two Wires

This USB HSIC standard, supporting high-speed data transfer rates, leverages the availability and knowledge of existing USB infrastructure to make connections between chips on a PCB or inside a multichip module. HSIC enables inter-chip connectivity by providing USB PHY implementations while eliminating cables and the analog component in the PHY. It operates at low-voltage CMOS levels and the interface is quite simplejust two wires. (See Figure 1.) It saves power and minimizes costs by removing the need to support the traditional USB 2.0 Full Speed and Low Speed protocols.

Complementing the USB HSIC standard is the USB Link Power Management (LPM) standard, which implements a new power sleep state to reduce power consumption. The USB LPM IP can provide faster suspend and resume times by three orders of magnitude (now microseconds instead of milliseconds) compared to the existing USB 2.0 specification, allowing devices to save power by more frequently turning off the USB connection while idle. In Figure 2 the diagram shows that DesignWare USB 2.0 nanoPHY in 45nm LP process Technology requires 50% less power than the previous generation with small area, low jitter & high yield.

Figure 2: DesignWare USB 2.0 nanoPHY Eye Diagram in 45nm LP Process Technology

Last fall, the USB 3.0 Promoter Group announced that the specification was completed and open to hardware developers. Delivering effective data rates exceeding 320 Mbytes/second (over 10 times the speed of today’s effective throughput connection) USB 3.0 will be backwards compatible with the previous USB technologies and is optimized for low power and improved protocol efficiency. As next generation PC, consumer and mobile devices demand faster data transfer with file size increases of up to 25 Gigabytes and beyond, designers will be looking to deploy the USB 3.0 IP into their integrated circuits now. Commercial products are expected to be released in late 2009 or early 2010.

There is a broad range of USB IP available for both wired and wireless USB applications. Companies like Synopsys work closely with major foundries to deliver silicon-proven IP that offer excellent yield and provide many features that simplify integration. Designers have an opportunity to use a complete portfolio of USB verification, digital controller, and mixed-signal PHY IP. The company has worked with desigers to successfully produce over 300 USB-enabled designs that have shipped an estimated 500 million products.

Gervais Fong is a Senior Product Manager for Mixed-Signal PHY IP at Synopsys. He has over 15 years of experience holding product marketing and product management positions covering ASIC, FPGA, EDA, and IP products. Gervais holds a Bachelor of Science degree in Electrical Engineering and Computer Science from the University of California, Berkeley. For more information on DesignWare USB IP, visit www.synopsys.com/usb