OpenVPX For High-Speed System Architectures



The third release of the OpenVPX standard will allow system designers to build the latest high-speed systems using the next generation of SBCs, switches and backplanes.

The third release of the OpenVPX standard will allow system designers to build the latest high-speed systems using the next generation of SBCs, switches and backplanes. The updated standard supports the transition to embedded 10 Gbit Ethernet and new radial clock techniques necessary for high performance analog and digital systems. And OpenVPX provides the module and slot profile definitions to support open systems development as well as a means to develop standard, interoperable, off-the-shelf payload modules.

Figure 1:  A backplane profile (BKP3-TIM12-15.3.6-n) has been created to test many of these new features in the U.S. Army’s CMOSS (C4ISR/EW Modular Open Suite of Standards) architecture.

Its technology trends that are driving the recent changes to the OpenVPX standard. New SBCs and Ethernet switches incorporate data rates that require backplanes to operate at 8 G/T per second for PCIe Gen 3, and up to 10 Gbaud for 10GBASE-KR Ethernet. In the case of Ethernet, the rates have increased from 3.125 Gb to 10.3125 Gb per lane.

Major Updates in Third Revision of OpenVPX
To handle this significant speed increase, new backplane designs that addresses the higher signaling rates of 8 Gb/sec for PCIe Gen3, and 10 and 40 Gb/s for Ethernet are required. This has led to the third major release of OpenVPX, which is now comprised of two documents.

The primary specification information is contained in one document, VITA 65.0, and the additional slot and module definitions have been moved to VITA 65.1.

Updates to for the PCIe and Ethernet protocols were only one aspect of the revisions. Backplanes supporting high speed Control and Data planes and highpower VITA 62 power supply slots have also been included. Other additions to accommodate system speed increases are updated I/O connectors (addressed by the VITA 66.x and 67.x standards) that support both RF and fiber optic I/O using MT ferrules; and the Ref Clock, which has increased from 10 MHz to 100 MHz.

Radial clock lines provide a means for a more accurate skew-adjusted clock and a defined timing Board profile, SLT3x-TIM-4S16S1U2U1H-14.9.1-n, which allows for a central source of the radial clock.

Although developed primarily in response to technology roadmaps showing that signaling rates for PCIe and Ethernet are rapidly increasing, OpenVPX’s recent enhancements took next-gen advancements into consideration, as well. This has secured its viability and usefulness throughout the many rugged military electronic systems that utilize this architecture.

Rugged Military Communications
Common military-related application areas that have implemented 3U OpenVPX since its inception more than seven years ago include Command, Control, Communications, Computers, Intelligence, Surveillance and Reconnaissance (C4ISR), Electronic Warfare (EW), radar, and network communications.

And, the technical standards bodies representing various branches of the military are increasingly encouraging open standards-based designs. The goal is mainly cross-branch interoperability, making OpenVPX a very attractive platform.

In fact, a backplane profile (BKP3-TIM12-15.3.6-n) has been created to test many of these new features in the U.S. Army’s CMOSS (C4ISR/EW Modular Open Suite of Standards) architecture. (Figure 1)

Paving the way for open architecture and multivendor interoperability, OpenVPX has opened up new definitions for VPX backplanes and systems and it enables a wide field of product choices for use in critical, high speed applications. This latest revision further underscores the longevity of standards.


Valerie Andrew is ‎Marketing Manager, Embedded Computing/Networking, Elma Electronic

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