August - 2016
- Choosing the best pin multiplexing method for your Multiple-FPGA partition
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July - 2016
- SRAM PUF:the Secure Silicon Fingerprint
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- New Guide: Understanding Vector Network Analysis
In this 62 page understanding guide we will introduce the basic fundamentals of the Vector Network Analyzer (VNA). Specific topics covered include phase and amplitude measurements, scattering parameters (S-parameters), and the polar and Smith chart displays.
- LTE vs LTE Advanced: What you need to know about carrier aggregation
The latest enhancement to LTE, known as LTE-Advanced or LTE-A, is an extensive set of new features that improve performance and increase reliability. Of these many features, carrier aggregation is perhaps the most important, because it simplifies traffic management while improving practical data rates and enhancing network capacity.
- Real User Monitoring for Performance-Based Global Traffic Management
Ensuring a speedy and consistent user experience becomes increasingly challenging as traffic grows. Several approaches attempt to tackle this problem, but only one succeeds. In this paper, Cedexis discusses the evolution that is happening in content delivery optimization â from single provider to round-robin based multiple origin to geo-based load balancing vs synthetic monitoring and real user monitoring, find out how you can evolve your content delivery strategy.
June - 2016
- A Guide to the MISRA Coding Standard: What you need to know
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May - 2016
- From Simulation to Emulation – A Fully Reusable UVM Framework
This paper introduces an acceleration-ready UVM framework and explains why it is needed, how to create it, and what its benefits are. By following the principles presented here, users will be able to write block-level UVM environments that can be reused directly in emulation. This approach has provided remarkable results in various customer environments, yielding a 50 to 5000X performance gain over pure simulation and significantly reducing testbench development time for emulation.
April - 2016
- High-Speed, Real-Time Recording Systems Handbook
In todayâs world of high-speed A/D converters operating in the gigahertz range, real-time signal recording has become a challenging task. When designing a real-time recorder capable of streaming sustained data to disk at rates of up to 3 GB/sec and higher, the developer has to consider the limitations presented by the operating and file systems, disk drive technology, the hardware interfaces, and the RAID controller technology. This handbook describes some of the features that are widely desired in such a system, including the use of a non-proprietary file system and the use of a client-server architecture.
- Optimizing Software Debug in Emulation
When debugging software on an emulator with a probe, something is always waiting. When the software developer is looking at memory, variables, and source code the emulator is occupied. With Codelink, most the waiting is eliminated as the developer interacts with a virtual target which is run on the same host as the debugger, eliminating the delays you get with a probe debugger. Because the virtual target is processing much less data than the original emulation, it can run faster â more than 10 times faster. This means 10 times less waiting for the developer. Download the paper to learn more.
March - 2016
- Where Does FAT Fail? - Exploring Compromises in this Ubiquitous File System Format.
As an early option for data organization, the FAT file system attained a certain ubiquity. This paper examines characteristics of the FAT file system that leave it vulnerable to corruption, and some ways vendors (including Microsoft) are trying to make it more reliable. Can reliability be achieved without sacrificing interoperability? Is the performance cost worth the benefit?
- Software Defined Radio Handbook
Software Defined Radio has revolutionized electronic systems for a variety of applications that include communications, data acquisition and signal processing. Recently updated, this
February - 2016
- Optimizing LPDDR4 Performance and Power with Multi-Channel Architectures
LPDDR4 offers huge bandwidth in a physically small PCB area and volume; up to 25.6 GByte/s of bandwidth at a 3,200 Mbps data rate from a single 15mmx15mm LPDDR4 package when two dies are packaged together. LPDDR4 builds on the success of LPDDR2 and LPDDR3 by adding new features and introducing a major architectural change. This white paper discusses why designers are selecting LPDDR4, how to handle 2-die and 4-die packages with multi-channel connections, the advantages of sharing channels through system-on-chip (SoC) partitioning, and how to optimize channels for the lowest power consumption.
- Delivering High Quality Analog Video Signals With Optimized Video DACs
In most modern consumer equipment, multimedia content is processed in the digital domain. However, analog video transmission requires the digital video content conversion to the analog domain. This white paper outlines the most common analog video signal standard-specifications that multimedia SoCs must support. It describes the key characteristics and features of a digital-to-analog converter solution optimized for video applications.
- Rapid Architectural Exploration in Designing Application-Specific Processors
Architectural exploration is at the heart of any ASIP design approach. This white paper explains the architectural tradeoffs available to an ASIP designer, such as performance vs. area, and why an ASIP design can still maintain full C-programmability while being optimized for a certain application domain.
- True Random Number Generators for Truly Secure Systems
Random numbers are at the heart of most security systems, yet methods for generating them vary in efficacy. Increasingly, many randomization algorithms and circuit implementations have been shown as flawed. This white paper examines current random number generation methods based on various entropy sources and associated attack techniques, including physical, statistical, and electronic methods.
- Addressing Three Critical Challenges of USB Type-C Implementation
As designers create new products and SoCs with USB Type-C support, they need to be aware of partitioning challenges. The SoC and system design must be partitioned to support the specificationâs requirements for precision analog circuitry plus high voltage/high current switches, and Type-C management software must be partitioned to execute on the processor, internal microcontroller, microcontroller in a power management IC, and/or on an external dedicated USB Type-C chip. This white paper describes key challenges and suggests solutions for designers of USB Type-C products and SoCs with native USB Type-C support.
- Designing an Efficient DSP Solution: Choosing the Right Processor and Software Development Toolchain
Read about key challenges in DSP implementation from both hardware and software application perspectives, and learn how a properly selected and configured DSP processor coupled with an advanced software development toolchain can overcome these challenges. This white paper describes how to generate tight, efficient, and maintainable DSP code for a platform consisting of an IP core based on a specialized instruction-set architecture (ISA) coupled with a DSP-aware toolchain.
- Developing Secure Embedded Software: Quality Doesn’t Equal Security
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December - 2015
- Advancing Intelligent Vending with the Internet of Things
Connected embedded platforms are enabling businesses to take advantage of the IoT. These intelligent systems improve all types of industrial applications, including those in the vending industry, which benefit from the sharing of information and insights. This white paper covers how ADLINKâs standard-based solutions help accelerate development of connected vending systems, delivering on the promise of connectivity, cloud services and analytics.
October - 2015
- Choosing the Right Cooling Methodology for OpenVPX™ Deployments
Which chassis cooling methodology is best for your application? This paper summarizes the basic chassis-level cooling methodologies that are commonly used with VPX: air, conduction, liquid, convection, heat exchangers and more. It provides you with the strengths and weaknesses of each methodology and offers guidance on which to choose.
- ATCA for Military, Aerospace and Other High Performance Embedded Computing Users
This paper addresses the forces driving the requirements of high performance embedded computing (HPEC) for military and aerospace applications, including the modular open system approach (MOSA), commercial-off-the-shelf (COTS), and reduced size, weight, power and cost (SWaP-C) as it applies to ATCA. The paper assumes a basic understanding of AdvancedTCA. An introduction to the technology is provided in the Artesyn Embedded Technologies white paper, "ATCA Yesterday, Today and Tomorrow."
- Image Pipeline Tuning - The Road to Ultimate Image Quality
This whitepaper is an introduction to image pipeline tuning for achieving best image quality for various combination of sensor and lens with varied lighting conditions in any camera based applications. It also covers issues with respect to image quality and care to be taken into consideration while evaluating the same.
September - 2015
- High-speed Switched Serial Fabrics Improve System Design
This handbook reviews the development of gigabit serial fabrics to enhance system optimization; the role of FPGAs to implement this technology; and how some of the latest products can be used in high-speed data acquisition, recording and SDR systems.
- Metadata Handling in Rugged Embedded Video Compression Systems
In many situations, information is useless without information about the information. Thatâs where metadata comes in: it can give context and meaning to, for example, captured video. This white paper describes how a recent update to the highly flexible architecture of GEâs ICS-8580 video compression board uniquely provides it with a metadata engine, making it substantially more powerful in its ability to deliver actionable intelligence.
- Knock Out Designs Quickly With Layout vs Schematic Comparison
Manage performance, database size and accuracy before, during and after design. Download your free whitepaper to learn how the new Calibre nmLVS boxing capabilities help manage these trade-offs by allowing:
- Proper usage of regular, black and gray boxing options including strict hierarchy preservation on the black and gray boxed cells
- Management of IP, missing IP and incomplete blocks during design development
- Running of circuit verification and downstream processes ensuring IP and macro cell blocks hierarchy are not altered
July - 2015
- Gaining Precision in Space Applications: Using Voltage References for Precision Signal Paths
Often when selecting a component in the signal path of a satellite system, it is difficult to find a device with the radiation tolerance and the accuracy required. Signal integrity
June - 2015
- Using an Embedded Vision Processor to Build and Efficient Object Recognition System
The advent of high-performance mobile computing platforms is driving rapid progress in computer vision capabilities. Machine vision is becoming embedded in highly integrated SoCs and
- RAR-XMC Capabilities Overview
In dynamic development and production test environments where multiple flight computers are supported, patch panels have been the typical implementation for migrating between different
- The Intelligent Flexible Cloud White Paper
This ARM white paper describes "The Intelligent Flexible Cloud" which is enabled by new technology standards, heterogeneous system on chip (SoC) architectures, and distribution of
- Selecting a Bus Analyzer 101
As avionics buses on military and commercial aircraft become more varied and complex, a bus analyzer has become an important tool for use during integration, validation, deployment,